CN204289464U - 一种高压pmos器件 - Google Patents

一种高压pmos器件 Download PDF

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CN204289464U
CN204289464U CN201420802695.0U CN201420802695U CN204289464U CN 204289464 U CN204289464 U CN 204289464U CN 201420802695 U CN201420802695 U CN 201420802695U CN 204289464 U CN204289464 U CN 204289464U
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pmos device
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吉扬永
连延杰
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本申请公开了一种高压PMOS器件，所述高压PMOS器件包括P型衬底、N型埋层、外延层、场氧、低压P阱、N阱、厚栅氧、薄栅氧、多晶硅栅、N型重掺杂区、第一P型重掺杂区、以及第二P型重掺杂区，其中，所述N阱和所述低压P阱的间矩为0.5μm～1μm。所述高压PMOS器件减少了工艺制作的掩膜，降低了成本。

Description

一种高压PMOS器件
技术领域
本实用新型涉及半导体器件，更具体地说，本实用新型涉及电子电路中的PMOS(P型金属氧化物半导体)器件。
背景技术
BCD(Bipolar CMOS DMOS)工艺通常采用重掺杂漏区和轻掺杂漏区相结合的方式来形成双扩散漏区以制作高压PMOS器件。相比于普通器件中只需采用一张掩膜即可形成漏区，高压PMOS器件需采用两张掩膜来形成双扩散漏区。为了节省掩膜，低压器件制作过程中用以形成P阱的掩膜可用于形成高压PMOS器件中的轻掺杂漏区。但是，相比于高压PMOS器件中的轻掺杂漏区，低压器件中的P阱的浓度显得太高，将严重影响高压PMOS器件的击穿电压，导致其值较低，影响高压PMOS器件的性能。
实用新型内容
考虑到现有技术的一个或多个技术问题，提出了一种高压PMOS器件，利用低压器件中采用的掩膜制作轻掺杂漏区和N阱，节省了掩膜，降低了成本，并且同时具有较高的击穿电压和较低的导通电阻。
根据本技术的实施例，提出了一种高压PMOS器件，包括：P型衬底；位于P型衬底上的N型埋层；位于N型埋层上的外延层；位于外延层上的场氧；位于外延层内的低压P阱；位于外延层内的N阱；位于低压P阱和场氧上的厚栅氧；位于N阱、低压P阱和外延层上的薄栅氧；位于薄栅氧和厚栅氧上的多晶硅栅；位于N阱内的N型重掺杂区，用作体接触区；位于低压P阱内的第一P型重掺杂区，所述第一P型重掺杂区与场氧毗邻；以及位于N阱内的第二P型重掺杂区，所述第二P型重掺杂区与多晶硅栅毗邻，并且与N型重掺杂区电连接；其中，所述N阱和所述低压P阱的间矩为0.5μm～1μm。
在一个实施例中，所述厚栅氧的厚度区间为到
在一个实施例中，在所述多晶硅栅下方，厚栅氧的边缘与场氧的边缘间矩为0.3μm～0.5μm。
在一个实施例中，所述低压P阱的侧壁与厚栅氧的边缘间矩为0.1μm～0.2μm。
在一个实施例中，所述N阱采用应用于低压器件中的低压N阱制作而成。
在一个实施例中，所述场氧采用浅槽隔离工艺制作而成。
在一个实施例中，所述场氧采用硅局部氧化工艺制作而成。
在一个实施例中，所述多晶硅栅延伸至场氧上部。
附图说明
为了更好的理解本实用新型，将根据以下附图对本实用新型进行详细描述：
图1示出了根据本实用新型一实施例的高压PMOS器件100的纵向剖面示意图；
图2示出了根据本实用新型一实施例的高压PMOS器件200的纵向剖面示意图；
图3A～3I以剖面图的形式示意性地示出了根据本实用新型一实施例形成高压PMOS器件100的工艺流程；
图4A～4I以剖面图的形式示意性地示出了根据本实用新型一实施例形成高压PMOS器件200的工艺流程。
具体实施方式
下面将详细描述本实用新型的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本实用新型。在以下描述中，为了提供对本实用新型的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是：不必采用这些特定细节来实行本实用新型。在其他实例中，为了避免混淆本实用新型，未具体描述公知的电路、材料或方法。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本实用新型至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解，在此提供的附图都是为了说明的目的，并且附图不一定是按比例绘制的。应当理解，当称元件“连接到”或“耦接到”另一元件时，它可以是直接连接或耦接到另一元件或者可以存在中间元件。相反，当称元件“直接连接到”或“直接耦接到”另一元件时，不存在中间元件。相同的附图标记指示相同的元件。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
图1示出了根据本实用新型一实施例的高压PMOS器件100的纵向剖面示意图。在图1中，所述高压PMOS器件100包括：P型衬底101；位于P型衬底101上的N型埋层102；位于N型埋层102上的外延层103；位于外延层103上的场氧111；位于外延层103内的低压P阱104；位于外延层103内的N阱107；位于低压P阱104和场氧111上的厚栅氧112；位于N阱107、低压P阱104和外延层103上的薄栅氧105；位于薄栅氧105和厚栅氧112上的多晶硅栅106；位于N阱107内的N型重掺杂区110，用作体接触区；位于低压P阱104内的第一P型重掺杂区108(P+)，所述第一P型重掺杂区108与场氧111毗邻；以及位于N阱107内的第二P型重掺杂区109(P+)，所述第二P型重掺杂区109与多晶硅栅106毗邻，并且与N型重掺杂区110电连接；其中，N阱107和低压P阱104的间矩d1为0.5μm～1μm。
在一个实施例中，所述厚栅氧112的厚度区间为到所述厚栅氧112形成于所述薄栅氧105之前，并且覆盖低压P阱104和场氧111的部分区域。如图1所示，在多晶硅栅106下方，厚栅氧112的边缘与场氧111的边缘间矩d2为0.3μm～0.5μm。同时，低压P阱104的侧壁与厚栅氧112的边缘间矩d3为0.1μm～0.2μm。
在一个实施例中，N阱107由应用于低压器件(与高压PMOS集成在同一衬底上的低压MOSFET，电容或其他器件)中的低压N阱材料制作而成。
在先进BCD工艺中，双极器件、CMOS和DMOS，以及高压器件和低压器件通常都集成于同一芯片。在本实用新型实施例中，高压PMOS器件100中的低压P阱104作为双扩散漏区的轻掺杂区，是采用低压器件(如低压NMOS)中的阱区制作而成的。而在现有技术中，为了形成高压PMOS器件100中轻掺杂区，则需要增加额外的掩膜版。因此，本实用新型实施例省略了用于制作漏区轻掺杂区的额外的掩膜版。通常情况下，低压器件中的P阱材料的浓度要比传统高压PMOS器件中的轻掺杂漏区的浓度要高。如果单单以低压器件中的P阱材料来制作高压PMOS器件的轻掺杂漏区的话，将导致高压PMOS器件的击穿电压降低。在本实用新型实施例中，厚栅氧的加入有助于提高器件的击穿电压。同时，N阱107和低压P阱104的间矩d1被限制在0.5μm～1μm，也有利于提高器件的击穿电压。在一个实施例中，高压PMOS器件100的击穿电压高达40V。由于在先进BCD工艺中，制作DMOS需用到厚栅氧，因此在高压PMOS器件100中加入厚栅氧不会增加额外的掩膜或制作步骤。同时，本实用新型实施例中的高压PMOS器件100由于采用浓度相对较高的低压P阱制作轻掺杂漏区，高压PMOS器件100的导通电阻Ron将比传统的高压PMOS器件要低。
在图1中，场氧111采用浅槽隔离工艺制作而成。本领域普通技术人员应该知道，高压PMOS器件中的场氧也可能采用其他工艺制作。
图2示出了根据本实用新型一实施例的高压PMOS器件200的纵向剖面示意图。除了场氧结构外，所述高压PMOS器件200具有与高压PMOS器件100相类似的结构。所述高压PMOS器件200中的场氧211采用硅局部氧化(LOCOS)技术制作而成。同时，在高压PMOS器件200中，多晶硅栅106也覆盖场氧211。
与高压PMOS器件100类似，高压PMOS器件200中厚栅氧212的厚度区间为所述厚栅氧212形成于所述薄栅氧105之前，并且覆盖低压P阱104的部分区域。如图2所示，在多晶硅栅106下方，厚栅氧212的边缘与场氧211的边缘间矩d2为0.3μm～0.5μm。同时，低压P阱104的侧壁与厚栅氧212的边缘间矩d3为0.1μm～0.2μm。
图3A～3I以剖面图的形式示意性地示出了根据本实用新型一实施例形成高压PMOS器件100的工艺流程。
如图3A所示，所述工艺流程包括在衬底101上形成N型埋层102。
如图3B所示，所述工艺流程包括在N型埋层102上形成外延层103。本说明书附图只示出了高压PMOS器件的剖面示意图，而未示出同衬底上其它器件的结构。本领域普通技术人员应该知道，N型埋层102仅覆盖衬底101的部分区域。而外延层103则同时覆盖N型埋层102和衬底101中未被N型埋层102覆盖的区域。在一个实施例中，所述外延层103采用化学气相沉积法(CVD)、等离子体增强型化学气相沉积(PECVD)、原子层沉积(ALD)、液相外延和/或其他合适的沉积技术制作而成。在一个实施例中，所述外延层可能注入P型杂质。
如图3C所示，所述工艺流程包括在外延层103中形成场氧111。在图3C中，场氧111采用浅槽隔离工艺(STI)制作而成。在一个实施例中，所述场氧111可能采用湿法氧化技术制作而成。
如图3D所示，所述工艺流程包括在外延层103中先后形成低压P阱104和N阱107。所述低压P阱104与低压器件中的P阱结构一致，并且采用同一张掩膜同时制作。因此不需要增加额外的掩膜。为了提高高压PMOS器件的击穿电压，所述N阱107与所述低压P阱104的间矩需控制在0.5um～1um之间。
如图3E所示，所述工艺流程包括在低压P阱104和场氧111上形成厚栅氧112。由于与高压PMOS器件集成的DMOS中包含厚栅氧，因此在高压PMOS器件中增加厚栅氧并不需要增加额外的掩膜。在一个实施例中，厚栅氧112的厚度在到之间。厚栅氧可通过热氧化技术或沉积技术制作而成。
如图3F所示，所述工艺流程包括形成薄栅氧105。在一个实施例中，所述薄栅氧105可通过干法氧化技术制作而成。
如图3G所示，所述工艺流程包括在薄栅氧105和厚栅氧112上形成多晶硅栅106。
如图3H所示，所述工艺流程包括在N阱107中形成N型重掺杂区110。在一个实施例中，所述N型重掺杂区110可通过扩散技术或者离子注入技术制作而成。
如图3I所示，所述工艺流程包括在低压P阱104中形成第一P型重掺杂区108和在N阱107中形成第二P型重掺杂区109。在一个实施例中，所述第一P型重掺杂区108和所述第二P型重掺杂区109可通过扩散技术或者离子注入技术制作而成。
在一个实施例中，所述N阱107可被低压N阱替代。由于在与高压PMOS器件集成的低压器件中需用到低压N阱，因此这种替代可额外节省一张掩膜。
图4A～4I以剖面图的形式示意性地示出了根据本实用新型一实施例形成高压PMOS器件200的工艺流程。
如图4A所示，所述工艺流程包括在衬底101上形成N型埋层102。
如图4B所示，所述工艺流程包括在在N型埋层102上形成外延层103。本说明书附图只示出了高压PMOS器件的剖面示意图，而未示出同衬底上其它器件的结构。本领域普通技术人员应该知道，N型埋层102仅覆盖衬底101的部分区域。而外延层103则同时覆盖N型埋层102和衬底101中未被N型埋层102覆盖的区域。在一个实施例中，所述外延层103采用化学气相沉积法(CVD)、等离子体增强型化学气相沉积(PECVD)、原子层沉积(ALD)、液相外延和/或其他合适的沉积技术制作而成。在一个实施例中，所述外延层可能注入P型杂质。
如图4C所示，所述工艺流程包括在外延层103中先后形成低压P阱104和N阱107。所述低压P阱104与低压器件中的P阱结构一致，并且同时制作。因此不需要增加额外的掩膜。为了提高高压PMOS器件的击穿电压，所述N阱107与所述低压P阱104的间矩需控制在0.5um～1um之间。
如图4D所示，所述工艺流程包括在外延层103中形成场氧211。在一个实施例中，所述场氧211可能采用湿法氧化技术制作而成。
如图4E所示，所述工艺流程包括在低压P阱104上形成厚栅氧212。所述厚栅氧212与场氧211毗邻。由于与高压PMOS器件集成的DMOS中包含厚栅氧，因此在高压PMOS器件中增加厚栅氧并不需要增加额外的掩膜。在一个实施例中，厚栅氧112的厚度在到之间。厚栅氧可通过热氧化技术或沉积技术制作而成。当厚栅氧211通过沉积技术制作时，将同时覆盖场氧211。
如图4F所示，所述工艺流程包括形成薄栅氧105。在一个实施例中，所述薄栅氧105可通过干法氧化技术制作而成。
如图4G所示，所述工艺流程包括在薄栅氧105、厚栅氧212以及场氧211上形成多晶硅栅106。
如图4H所示，所述工艺流程包括在N阱107中形成N型重掺杂区110。在一个实施例中，所述N型重掺杂区110可通过扩散技术或者离子注入技术制作而成。
如图4I所示，所述工艺流程包括在低压P阱104中形成第一P型重掺杂区108和在N阱107中形成第二P型重掺杂区109。在一个实施例中，所述第一P型重掺杂区108和所述第二P型重掺杂区109可通过扩散技术或者离子注入技术制作而成。
在一个实施例中，所述N阱107可被低压N阱替代。由于在与高压PMOS器件集成的低压器件中需用到低压N阱，因此这种替代可额外节省一张掩膜。
本实用新型提供了高压PMOS器件的结构和制作工艺流程的几个实施例。与传统的高压PMOS器件相比，本实用新型实施例提供的高压PMOS器件采用低压器件中的P阱制作双扩散漏区中的轻掺杂漏区，节省了制作轻掺杂漏区所需的掩膜，并且降低了器件的导通电阻。同时，本实用新型实施例提供的高压PMOS器件增加了DMOS器件中的厚栅氧，来提高器件的击穿电压。本实用新型实施例中的高压PMOS器件的N阱可采用低压器件中的低压N阱来制作，以进一步节省掩膜。
虽然已参照几个典型实施例描述了本实用新型，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本实用新型能够以多种形式具体实施而不脱离实用新型的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (8)

1.一种高压PMOS器件，包括：
P型衬底；
位于P型衬底上的N型埋层；
位于N型埋层上的外延层；
位于外延层上的场氧；
位于外延层内的低压P阱；
位于外延层内的N阱；
位于低压P阱和场氧上的厚栅氧；
位于N阱、低压P阱和外延层上的薄栅氧；
位于薄栅氧和厚栅氧上的多晶硅栅；
位于N阱内的N型重掺杂区，用作体接触区；
位于低压P阱内的第一P型重掺杂区，所述第一P型重掺杂区与场氧毗邻；以及
位于N阱内的第二P型重掺杂区，所述第二P型重掺杂区与多晶硅栅毗邻，并且与N型重掺杂区电连接；
其中，所述N阱和所述低压P阱的间矩为0.5μm～1μm。
2.如权利要求1所述的高压PMOS器件，其中所述厚栅氧的厚度区间为到
3.如权利要求1所述的高压PMOS器件，在所述多晶硅栅下方，厚栅氧的边缘与场氧的边缘间矩为0.3μm～0.5μm。
4.如权利要求1所述的PMOS器件，所述低压P阱的侧壁与厚栅氧的边缘间矩为0.1μm～0.2μm。
5.如权利要求1所述的高压PMOS器件，所述N阱采用应用于低压器件中的低压N阱制作而成。
6.如权利要求1所述的高压PMOS器件，所述场氧采用浅槽隔离工艺制作而成。
7.如权利要求1所述的高压PMOS器件，所述场氧采用硅局部氧化工艺制作而成。
8.如权利要求7所述的高压PMOS器件，所述多晶硅栅延伸至场氧上部。
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