CN105489481B - 一种阶梯型厚栅氧化层的制作方法 - Google Patents

一种阶梯型厚栅氧化层的制作方法 Download PDF

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CN105489481B
CN105489481B CN201610018432.4A CN201610018432A CN105489481B CN 105489481 B CN105489481 B CN 105489481B CN 201610018432 A CN201610018432 A CN 201610018432A CN 105489481 B CN105489481 B CN 105489481B
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oxide layer
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CN105489481A (zh
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连延杰
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

公开了一种阶梯型厚栅氧化层的制作方法。该制作方法可以减少阶梯型厚栅氧化层制作工艺中的掩膜数，降低高压BCD工艺中高压器件的制作成本。此外，采用该制作方法，阶梯型厚栅氧化层的尺寸易于控制，有利于改善整个高压器件的性能，且厚栅氧化层的总厚度可以达到3000埃以上，可承受更高的电压。

Description

一种阶梯型厚栅氧化层的制作方法
技术领域
本发明涉及半导体器件的制造，更具体地，本发明涉及一种高压BCD工艺中阶梯型厚栅氧化层的制作方法。
背景技术
在高压BCD(双极型-互补金属氧化半导体-双扩散金属氧化半导体，Bipolar-CMOS-DMOS)工艺的集成电路结构中，通常需要厚栅氧化层来制作高压MOS器件。与具有传统厚栅氧化层的高压MOS器件相比，具有阶梯型厚栅氧化层的高压MOS器件可减小导通电阻，有效削弱栅极下方的漏端表面电场以提高击穿电压。现有技术中阶梯型厚氧化层的制作工艺为：利用掩膜1淀积出传统厚栅氧化层之后，再利用掩膜2对传统厚栅氧化层进行蚀刻以形成台阶。然而，通过上述工艺制作的阶梯型厚栅氧化层的厚度一般只有1000埃左右，不能承受足够的电压，影响整个高压器件的性能。此外，该制作方法成本较高，制约着半导体器件集成的发展。
发明内容
考虑到现有技术的一个或多个技术问题，提出了一种既节约成本又便于调整尺寸的阶梯型厚栅氧化层的制作方法，从而更好地为高压BCD工艺的器件性能提供保证。
根据上述目的，本发明提出了一种阶梯型厚栅氧化层的制作方法，包括：在半导体衬底上形成第一衬垫氧化层；在第一衬垫氧化层上形成氮化层；在氮化层上形成第二衬垫氧化层；在第二衬垫氧化层上淀积多晶硅；通过掩膜开口从多晶硅的露出面开始蚀刻，制作贯穿多晶硅的多晶硅开口；从第二衬垫氧化层的露出面开始蚀刻，制作贯穿第二衬垫氧化层的氧化层开口；从氮化层的露出面开始蚀刻，制作贯穿氮化层的氮化层开口，其中氮化层开口的宽度大于氧化层开口的宽度；向氮化层开口、氧化层开口以及多晶硅开口构成的阶梯型沟槽内淀积填充氧化物；去除淀积在多晶硅表面的填充氧化物；去除剩余的多晶硅；去除剩余的第二衬垫氧化层；去除剩余的氮化层；以及去除暴露的第一衬垫氧化层。
根据上述制作方法，不仅节省了掩膜，降低了成本，同时在制作过程中，阶梯型厚栅氧化层的尺寸易于控制，有利于改善整个高压器件的性能。
附图说明
为了更好的理解本发明，将根据以下附图对本发明进行详细描述：
图1-13示出了根据本发明一实施例的阶梯型厚栅氧化层108的制作流程图；
图14和15分别示出了阶梯型厚栅氧化层108制作完成后薄栅氧化层109与多晶硅栅110的制作流程图；
图16示出了根据本发明一实施例的阶梯型厚栅氧化层制作方法300的流程图。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在以下描述中，为了提供对本发明的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是：不必采用这些特定细节来实行本发明。在其他实例中，为了避免混淆本发明，未具体描述公知的电路、材料或方法。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解，在此提供的附图都是为了说明的目的，并且附图不一定是按比例绘制的。
图1-13示出了根据本发明一实施例的阶梯型厚栅氧化层108的制作流程图，下面结合附图详细描述本发明的具体实施例方式。
如图1所示，在半导体衬底101上形成第一衬垫氧化层102。第一衬垫氧化层102可保护半导体衬底101(例如硅)表面免受随后工艺引发的机械压力影响，可通过热氧化技术或淀积技术制作而成。在一个实施例中，第一衬垫氧化层102的材料为二氧化硅，厚度区间为
如图2所示，在第一衬垫氧化层102上形成氮化层103。在一个实施例中，氮化层103通过淀积技术制作而成，例如化学气相淀积技术。在一个实施例中，氮化层103的材料为Si3N4。在一个实施例中，氮化层103的厚度等于阶梯型厚栅氧化层108下级台阶的厚度，其厚度区间为
如图3所示，在氮化层103上形成第二衬垫氧化层104。可采用任何已知的方法来制作第二衬垫氧化层104，例如热生长、淀积等。
如图4所示，在第二衬垫氧化层104上淀积多晶硅105。淀积多晶硅105可以采用任何已知的淀积方法。多晶硅105的厚度与阶梯型厚栅氧化层108的厚度有关。多晶硅105的厚度区间可以但不限于
如图5所示，在多晶硅105上方放置具有开口1060的掩膜106，通过掩膜106的开口1060蚀刻多晶硅105，以制作贯穿多晶硅105的多晶硅开口1050。在一个实施例中，采用干法蚀刻技术来蚀刻多晶硅105，例如反应离子刻蚀、等离子刻蚀和化学气相刻蚀等。在一个实施例中，采用各向异性蚀刻技术来蚀刻多晶硅105，以形成如图5所示的接近垂直的侧壁。多晶硅开口1050与掩膜开口1060具有同样的宽度L1。宽度L1根据MOS器件的性能要求(例如击穿电压和/或其他合适的MOS器件参数)来确定。
接下来，如图6所示，采用干法或湿法蚀刻等蚀刻技术通过多晶硅105的开口1050来蚀刻第二衬垫氧化层104，形成贯穿于第二衬垫氧化层104的氧化层开口1040，使氮化层103的表面露出宽度为L2的区域。在一个实施例中，宽度L2等于多晶硅开口1050的宽度L1。在图示的实施例中，宽度L2大于多晶硅开口1050的宽度L1，可采用各向同性蚀刻或者其他合适的过蚀刻技术来蚀刻第二衬垫氧化层104。
如图7所示，从氮化层103的露出面开始蚀刻，制作贯穿氮化层103的氮化层开口1030，使第一衬垫氧化层102的表面露出宽度为L3的区域。氮化层开口1030的宽度L3大于氧化层开口1040的宽度L2，可采用各向同性蚀刻或者其他合适的过蚀刻技术来蚀刻氮化层103。在一个实施例中，用热磷酸或其他刻蚀液以保证在刻蚀氮化层103的同时，不刻蚀多晶硅105与第一衬垫氧化层102和第二衬垫氧化层104，从而实现较好的刻蚀选择比。在一个实施例中，宽度L2与L3受蚀刻条件，例如蚀刻时间的控制。
接下来，如图8所示，向由多晶硅开口1050、氧化层开口1040以及氮化层开口1030构成的阶梯型沟槽内填充氧化物，形成填充氧化层107，可采用任何已为我们熟知的技术来填充。在一个实施例中，填充氧化物是正硅酸乙酯(TEOS)、硼磷硅玻璃(BPSG)或者其它常用于作层间介质材料的氧化物。在一个实施例中，采用高温回流技术和增稠技术来保证填充氧化层107的均匀性和硬度，以提高性能。
填充氧化物可能被淀积太多，从而部分淀积于多晶硅105的上表面。如图9所示，将淀积于多晶硅105上表面的填充氧化物移除。移除多余填充氧化物的方法既可以是空白蚀刻，也可以是化学机械研磨(Chemical Mechanical Polish，CMP)等方法。在进一步的实施例中，为使多晶硅105和填充氧化层107表面平坦，还将采用机械或化学抛光工艺。在一个实施例中，可通过上述抛光工艺控制多晶硅105和填充氧化层107的厚度，以便于调整阶梯型厚栅氧化层108上级台阶的厚度。
如图10所示，移除剩余的多晶硅105，可采用本技术领域中的任何蚀刻方法，或者任何其他可用于移除多晶硅的技术，例如干法蚀刻。
如图11所示，移除剩余的第二衬垫氧化层104。由于填充氧化层107与第二衬垫氧化层104的材料同为氧化物，因此，填充氧化层107的一部分露出面也会随第二衬垫氧化层104一起被移除，形成填充氧化层107A。在进一步的实施例中，填充氧化层107A的厚度可通过上述移除步骤来控制。在一个实施例中，填充氧化层107A的厚度等于填充氧化层107与第二衬垫氧化层104的厚度之差。在另一个实施例中，填充氧化层107A的厚度小于填充氧化层107与第二衬垫氧化层104的厚度之差。
如图12所示，移除剩余的氮化层103，可采用蚀刻、剥离、溶解等方法。在一个实施例中，采用热磷酸溶液来移除剩余的氮化层103。
如图13所示，移除暴露的第一衬垫氧化层102。与图11相同，填充氧化层107A的露出面也会被移除一部分，形成填充氧化层107B。在进一步的实施例中，填充氧化层107B的厚度可通过上述移除步骤来控制，以控制阶梯型厚栅氧化层108的最终厚度。在一个实施例中，填充氧化层107B的厚度等于填充氧化层107A与第一衬垫氧化层102的厚度之差。在另一个实施例中，填充氧化层107B的厚度小于填充氧化层107A与第一衬垫氧化层102的厚度之差。
至此，由位于填充氧化层107B下方的第一衬垫氧化层102和填充氧化层107B构成的阶梯型厚栅氧化层108被制作完成，其最终厚度等于第一衬垫氧化层102与填充氧化层107B的厚度之和。
阶梯型厚栅氧化层108的厚度与MOS器件的电压等级有关，可根据不同的电压需求作相应的调整。在一个实施例中，阶梯型厚栅氧化层108的最终厚度选用能够实现高压MOS器件所需电压的最小厚度。随着所需电压的增大，阶梯型厚栅氧化层108的厚度也随之增加。
在本发明的一个实施例中，阶梯型厚栅氧化层108下级台阶的厚度由氮化层103的厚度控制，上级台阶的厚度可在图9描述的抛光工艺、图11以及图13的去除步骤中进行调整。此外，上级台阶的宽度由宽度L1控制，下级台阶的宽度由宽度L3与L1共同控制。因此，采用本发明的制作方法，可以非常方便的控制阶梯型厚栅氧化层108的尺寸，以满足不同电压的需求。根据本发明的制作方法，阶梯型厚栅氧化层108的厚度可达到以上，可实现45V～60V乃至更高的电压。与现有技术的制作方法相比，可以承受更高的电压等级。
此外，在本发明的制作流程中，只有图8中对多晶硅105的蚀刻需要掩膜。与现有的制作方法相比，采用本发明的制作方法可以节省掩膜、降低成本。
随后，如图14所示，MOS器件的制作工序还包括在没有覆盖厚栅氧化层108的区域生长一层非常薄的、高质量的栅氧化物，形成薄栅氧化层109。进一步地，如图15所示，在厚栅氧化层108和薄栅氧化层109上的形成多晶硅栅110。此外，MOS器件的制作工序还包括在多晶硅栅110上继续形成金属氧化物等其他工序等，为了本发明清楚的目的，在此不再一一赘述。
图16示出了根据本发明一实施例的阶梯型厚栅氧化层制作方法300的流程图。制作方法300包括步骤302～326。
在步骤302，在半导体衬底上形成第一衬垫氧化层。
在步骤304，在第一衬垫氧化层上形成氮化层。
在步骤306，在氮化层上形成第二衬垫氧化层。
在步骤308，在第二衬垫氧化层上淀积多晶硅。
在步骤310，通过掩膜开口从多晶硅的露出面开始蚀刻，制作贯穿多晶硅的多晶硅开口。
在步骤312，从第二衬垫氧化层的露出面开始蚀刻，制作贯穿第二衬垫氧化层的氧化层开口。在一个实施例中，氧化层开口的宽度大于多晶硅开口的宽度。在另一个实施例中，氧化层开口的宽度等于多晶硅开口的宽度。
在步骤314，从氮化层的露出面开始蚀刻，制作贯穿氮化层的氮化层开口，其中氮化层开口的宽度大于氧化层开口的宽度。
在步骤316，向氮化层开口、氧化层开口以及多晶硅开口构成的阶梯型沟槽内淀积填充氧化物。
在步骤318，去除淀积在多晶硅表面的填充氧化物。
在步骤320，去除剩余的多晶硅。
在步骤322，去除剩余的第二衬垫氧化层。
在步骤324，去除剩余的氮化层。
在步骤326，去除暴露的第一衬垫氧化层。
在一个实施例中，制作方法300还包括步骤319，采用机械或化学抛光工艺控制多晶硅与填充氧化物的厚度，以控制阶梯型厚栅氧化层的厚度。
需要说明的是，其他实施例所包括的步骤可能比制作方法300所包括的步骤多，也可能比制作方法300所包括的步骤少。
虽然已参照几个典型实施例描述了本发明，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (10)

1.一种阶梯型厚栅氧化层的制作方法，包括：
在半导体衬底上形成第一衬垫氧化层；
在第一衬垫氧化层上形成氮化层；
在氮化层上形成第二衬垫氧化层；
在第二衬垫氧化层上淀积多晶硅；
通过掩膜开口从多晶硅的露出面开始蚀刻，制作贯穿多晶硅的多晶硅开口；
从第二衬垫氧化层的露出面开始蚀刻，制作贯穿第二衬垫氧化层的氧化层开口；
从氮化层的露出面开始蚀刻，制作贯穿氮化层的氮化层开口，其中氮化层开口的宽度大于氧化层开口的宽度；
向氮化层开口、氧化层开口以及多晶硅开口构成的阶梯型沟槽内淀积填充氧化物；
去除淀积在多晶硅表面的填充氧化物；
去除剩余的多晶硅；
去除剩余的第二衬垫氧化层；
去除剩余的氮化层；以及
去除暴露的第一衬垫氧化层；其中
剩余的第一衬垫氧化层和剩余的填充氧化层构成了阶梯型厚栅氧化层，所述阶梯型厚栅氧化层的厚度等于剩余的第一衬垫氧化层和填充氧化层的厚度之和。
2.如权利要求1所述的制作方法，其中氧化层开口的宽度大于多晶硅开口的宽度。
3.如权利要求1所述的制作方法，其中氧化层开口的宽度等于多晶硅开口的宽度。
4.如权利要求1所述的制作方法，其中该阶梯型栅氧化层具有两级台阶，该制作方法通过控制掩膜开口的宽度来控制上级台阶的宽度。
5.如权利要求4所述的制作方法，其中通过控制掩膜开口的宽度和氮化层开口的宽度来控制下级台阶的宽度。
6.如权利要求1所述的制作方法，进一步包括在去除剩余的第二衬垫氧化层和去除暴露的第一衬垫氧化层的步骤中，控制阶梯型厚栅氧化层的厚度。
7.如权利要求1所述的制作方法，其中填充氧化物为正硅酸乙酯。
8.如权利要求1所述的制作方法，其中制作多晶硅开口的方法包括各向异性蚀刻。
9.如权利要求1所述的制作方法，其中氮化层的厚度区间为 至
10.如权利要求1所述的制作方法，其中多晶硅的厚度区间为 至
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