CN100369204C - 利用双镶嵌工艺来制造t型多晶硅栅极的方法 - Google Patents
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Abstract
本发明提供一种利用双镶嵌工艺来制造T型多晶硅栅极的方法,它是在一半导体基底上形成一氧化层、一硬掩膜层,及一图案化第一光刻胶层,以图案化光刻胶层为掩膜,对硬掩膜层与氧化层进行刻蚀,来形成一第一沟槽,去除图案化第一光刻胶层,然后在第一沟槽沉积一有机层,在半导体基底上形成一图案化第二光刻胶层,以图案化第二光刻胶层对硬掩膜进行刻蚀,来定义出第二沟槽的尺寸,去除图案化第二光刻胶层与有机层,在第一、第二沟槽内沉积一氧化层与一多晶硅层,去除剩余的硬掩膜层,得到一T形轮廓的多晶硅栅极。
Description
技术领域
本发明涉及一种形成T型多晶硅栅极的方法,特别涉及一种利用双镶嵌工艺来制造T型多晶硅栅极的方法。
背景技术
半导体组件和电路的组成以金属氧化物半导体场效应晶体管(MOSFET)为基础,金属氧化物半导体场效应晶体管组件以栅极(gate)作为控制电极,也就是以栅极的电压讯号控制晶体管输出特性。当半导体的工艺技术朝深亚微米(deep submicron)前进,使得组件的集成度增加而组件尺寸也随之减小,而当晶体管的源极/漏极浅沟道结(Shallow junction)时,主要参考的结构参数有(1)延伸区接面深度、(2)延伸区侧向长度、(3)延伸区侧向掺杂浓度分布等等。因此尺寸进入深亚微米级后,晶体管须具备有相对于通常的晶体管低的密勒电容(miller capacitance)值与较高的驱动电流,以获得良好的组件驱动性。因此在通常的技术中,为达到具有较高的驱动电流,与降低密勒电容,一般进行源/漏极延伸区的掺杂工艺(Source/Drain extension dopant)以获得较高的驱动电流。
但是在更进一步缩小组件尺寸的情况下,进行源/漏极延伸区的掺杂工艺时,掺杂物容易镶嵌在多晶硅栅极边缘,导致多晶硅栅极边缘较易击穿。
因此,本发明提出一种利用双镶嵌工艺来制造T型多晶硅栅极的方法,不仅可以解决上述的问题,而且本发明可以通过制造过程中减少并控制栅极线宽,同时达到提高组件的集成度的目的。
发明内容
本发明的主要目的,在于提供一种利用双镶嵌工艺来制造T型多晶硅栅极的方法,它能够有效的防止进行源/漏极延伸区的掺杂工艺时,掺杂物镶嵌在多晶硅栅极边缘,而导致多晶硅栅极边缘击穿电压较低的情况。
本发明的另一目的,在于提供一种利用双镶嵌工艺来制造T型多晶硅栅极的方法,它具有较小的栅极线宽,进而达到增加组件的集成度。
为了达到上述的目的,本发明提供一种利用双镶嵌工艺来制造T型多晶硅栅极的方法,它包括下列步骤:提供一内部形成有隔离区域的半导体基底;在半导体基底上依序形成一氧化层,一硬掩膜层,及一图案化第一光刻胶层,接着,以图案化第一光刻胶层为掩膜,对硬掩膜层与氧化层进行刻蚀工艺,直至暴露出半导体基底为止,来形成一第一沟槽,而后去除图案化第一光刻胶层;在第一沟槽沉积一有机层,对有机层进行一回刻蚀工艺,直至有机层的表面高度低于硬掩膜层为止;在半导体基底上形成一图案化第二光刻胶层,且图案化第二光刻胶层定义出所要刻蚀的第二沟槽尺寸,而图案化第二光刻胶层的刻蚀窗尺寸大于所述第一沟槽,以图案化第二光刻胶层为掩膜,对硬掩膜层继续进行一次刻蚀工艺,来形成一第二沟槽,而后去除图案化第二光刻胶层与有机层;对半导体基底进行一次氧化工艺,使从第一沟槽暴露出的半导体基底表面形成一栅极氧化层;在半导体基底上沉积一多晶硅层,并填满第一、第二沟槽,而后对多晶硅层进行一平整化工艺;以及去除剩余的硬掩膜层,然后以多晶硅层为掩膜去除暴露出的氧化层,以得到一T型轮廓的多晶硅栅极。
本发明的有益效果是:它能够有效地防止进行源/漏极延伸区的掺杂工艺时,掺杂物镶嵌在多晶硅栅极边缘,而导致多晶硅栅极边缘击穿电压较低的情况,同时由于具有较小的栅极线宽,可以进一步增加组件的集成度。
附图说明
图1至图7为本发明的各步骤构造剖视图。
标号说明:
10半导体基底
12氧化层
14硬掩膜层
16图案化第一光刻胶层
18第一沟槽
20有机层
22图案化第二光刻胶层
24第二沟槽
26栅极氧化层
28多晶硅层
具体实施方式
以下结合附图及实施例进一步说明本发明的结构特征及所达成的有益效果。
本发明提供了一种利用双镶嵌工艺来制造T型多晶硅栅极的方法,图1至图7是本发明的一个较佳实施例的各步骤构造剖视图。
首先请参阅图1,在一内部已形成有数个隔离区域(图中未示)的半导体基底10上依序形成一氧化层12,一硬掩膜层14,以及一图案化第一光刻胶层16,其中硬掩膜层14的材质可以是氮氧化硅(SiON)或四乙氧基硅烷(TEOS)等其它材质,并以低压化学气相沉积法沉积而得。然后,以图案化第一光刻胶层16为掩膜,对硬掩膜层14与氧化层12进行一刻蚀工艺,直至暴露出半导体基底10为止,以形成一第一沟槽18,而后去除图案化第一光刻胶层16,形成如图2所示的结构。
接着,如图3所示,利用涂布的方式(spin coating)在第一沟槽18沉积一有机层20,其中有机层20可以是有机抗反射层(BARC),然后,对有机层20进行一回刻蚀工艺(Etching Back),直至有机层20的表面高度低于硬掩膜层14为止。
再在半导体基底10上形成一图案化第二光刻胶层22,来定义出所要刻蚀的第二沟槽尺寸,且图案化第二光刻胶层22的刻蚀窗的尺寸大于第一沟槽,如图4所示的状态,然后以图案化第二光刻胶层22为掩膜,对硬掩膜层14继续进行一刻蚀工艺,以形成一第二沟槽24,而后去除图案化第二光刻胶层22与有机层20,而形成如图5所示的结构,此时因为有有机层20的保护使得第一沟槽18底部能维持将近直角。
接着,对半导体基底10进行一氧化工艺工艺,其中氧化工艺工艺是以氧气来进行快速氧化处理,因为快速氧化处理不会对硬掩膜层14产生作用,所以进行快速氧化处理之后,氧气等离子体仅会与自第一沟槽18暴露出的半导体基底10进行反应,形成一栅极氧化层26,然后,在半导体基底10上沉积一填满第一、第二沟槽18、24的多晶硅层28,对多晶硅层28进行一化学机械抛光工艺(CMP),来去除多余的多晶硅层28,以达到所谓的全面性平整化,形成如图6所示的结构。
最后,如图7所示,去除剩余的硬掩膜层14,然后以多晶硅层28为掩膜,去除未覆盖多晶硅层28的氧化层12,以得到一T型轮廓的多晶硅栅极。
本发明的多晶硅栅极,不但具有较小的栅极线宽,而可以增加组件的集成度,更能够有效的防止进行源/漏极延伸区的掺杂工艺时,掺杂物镶嵌在多晶硅栅极边缘,而导致多晶硅栅极边缘击穿电压较低的情况。
以上所述的实施例仅为了说明本发明的技术思想及特点,其目的在使本领域的普通技术人员能够了解本发明的内容并据以实施,本专利的范围并不仅局限于上述具体实施例,即凡依本发明所揭示的精神所作的同等变化或修饰,仍涵盖在本发明的保护范围内。
Claims (7)
1.一种利用双镶嵌工艺来制造T型多晶硅栅极的方法,包括下列步骤:
提供一半导体基底,其内部形成有隔离区域;
在所述半导体基底上依序形成一氧化层,一硬掩膜层,及一图案化第一光刻胶层,以所述图案化第一光刻胶层为掩膜,对所述硬掩膜层与所述氧化层进行刻蚀工艺,直至暴露出所述半导体基底为止,以形成一第一沟槽,而后去除所述图案化第一光刻胶层;
在所述第一沟槽沉积一有机层,对所述有机层进行一回刻蚀工艺,至所述有机层的表面高度低于所述硬掩膜层为止;
在所述半导体基底上形成一图案化第二光刻胶层,以定义出所要刻蚀的第二沟槽尺寸,而所述图案化第二光刻胶层的刻蚀窗尺寸大于所述第一沟槽,以所述图案化第二光刻胶层为掩膜,对所述硬掩膜层继续进行一刻蚀工艺,以形成一第二沟槽,而后去除所述图案化第二光刻胶层与所述有机层;
对所述半导体基底施行一氧化工艺,使从所述第一沟槽暴露出的所述半导体基底表面形成一栅极氧化层;
在所述半导体基底上沉积一多晶硅层,并填满所述第一、第二沟槽,而后对所述多晶硅层进行一平整化工艺;以及
去除剩余的所述硬掩膜层,然后以所述多晶硅层为掩膜去除暴露出的所述氧化层,以得到一T型轮廓的多晶硅栅极。
2.根据权利要求1所述的利用双镶嵌工艺来制造T型多晶硅栅极的方法,其特征在于:所述硬掩膜层的材质为氮氧化硅或四乙氧基硅烷。
3.根据权利要求1所述的利用双镶嵌工艺来制造T型多晶硅栅极的方法,其特征在于:所述氧化工艺为快速氧化工艺。
4.根据权利要求3所述的利用双镶嵌工艺来制造T型多晶硅栅极的方法,其特征在于:所述快速氧化工艺是以氧气等离子体来进行处理。
5.根据权利要求1所述的利用双镶嵌工艺来制造T型多晶硅栅极的方法,其特征在于:所述平整化工艺为化学机械抛光法。
6.根据权利要求1所述的利用双镶嵌工艺来制造T型多晶硅栅极的方法,其特征在于:所述硬掩膜层是利用低压化学气相沉积而成。
7.根据权利要求1所述的利用双镶嵌工艺来制造T型多晶硅栅极的方法,其特征在于:所述有机层为有机抗反射层。
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US7332421B2 (en) * | 2003-12-31 | 2008-02-19 | Dongbu Electronics Co., Ltd. | Method of fabricating gate electrode of semiconductor device |
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CN101441996B (zh) * | 2007-11-21 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | 硬掩膜层的形成方法及刻蚀方法 |
CN102832123A (zh) * | 2011-06-14 | 2012-12-19 | 孙润光 | 一种功率电子开关器件及其制造方法 |
CN103943678B (zh) * | 2013-01-22 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法 |
US10340352B2 (en) | 2017-03-14 | 2019-07-02 | Globalfoundries Inc. | Field-effect transistors with a T-shaped gate electrode |
CN110333565A (zh) * | 2019-06-24 | 2019-10-15 | 武汉华星光电技术有限公司 | 金属纳米光栅及其纳米压印制备方法和显示装置 |
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US5688704A (en) * | 1995-11-30 | 1997-11-18 | Lucent Technologies Inc. | Integrated circuit fabrication |
US6077733A (en) * | 1999-09-03 | 2000-06-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing self-aligned T-shaped gate through dual damascene |
US6403456B1 (en) * | 2000-08-22 | 2002-06-11 | Advanced Micro Devices, Inc. | T or T/Y gate formation using trim etch processing |
US20030162406A1 (en) * | 2002-02-22 | 2003-08-28 | Gehoski Kathleen Ann | Method of fabricating a tiered structure using a multi-layered resist stack and use |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6245669B1 (en) * | 1999-02-05 | 2001-06-12 | Taiwan Semiconductor Manufacturing Company | High selectivity Si-rich SiON etch-stop layer |
US6541382B1 (en) * | 2000-04-17 | 2003-04-01 | Taiwan Semiconductor Manufacturing Company | Lining and corner rounding method for shallow trench isolation |
US7176138B2 (en) * | 2004-10-21 | 2007-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective nitride liner formation for shallow trench isolation |
-
2004
- 2004-05-19 CN CNB200410018450XA patent/CN100369204C/zh not_active Expired - Fee Related
-
2005
- 2005-04-05 US US11/098,495 patent/US20050260840A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5688704A (en) * | 1995-11-30 | 1997-11-18 | Lucent Technologies Inc. | Integrated circuit fabrication |
US6077733A (en) * | 1999-09-03 | 2000-06-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing self-aligned T-shaped gate through dual damascene |
US6403456B1 (en) * | 2000-08-22 | 2002-06-11 | Advanced Micro Devices, Inc. | T or T/Y gate formation using trim etch processing |
US20030162406A1 (en) * | 2002-02-22 | 2003-08-28 | Gehoski Kathleen Ann | Method of fabricating a tiered structure using a multi-layered resist stack and use |
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US20050260840A1 (en) | 2005-11-24 |
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