JP2013030780A - 低ノイズ及び高性能のlsi素子、レイアウト及びその製造方法 - Google Patents
低ノイズ及び高性能のlsi素子、レイアウト及びその製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 44
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 44
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 abstract description 51
- 150000002500 ions Chemical class 0.000 abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 229910052732 germanium Inorganic materials 0.000 abstract description 6
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 79
- 229910004298 SiO 2 Inorganic materials 0.000 description 21
- 239000000758 substrate Substances 0.000 description 19
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 17
- 229910052814 silicon oxide Inorganic materials 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 230000000694 effects Effects 0.000 description 10
- 230000001976 improved effect Effects 0.000 description 10
- 125000006850 spacer group Chemical group 0.000 description 10
- 238000000137 annealing Methods 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 239000010703 silicon Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000004151 rapid thermal annealing Methods 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 5
- 239000010941 cobalt Substances 0.000 description 5
- 229910017052 cobalt Inorganic materials 0.000 description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 229910004541 SiN Inorganic materials 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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Abstract
【解決手段】NMOS素子及びPMOS素子が何れもアナログ及びデジタルモードのような相異なるモードで動作される半導体素子において、これら素子の要求される動作モードによって特定素子にストレスエンジニアリングを選択的に適用する。フォトレジスト160をデジタル回路領域のPMOSトランジスタのみを覆うように形成し、Ge、Siなどのイオン162をストレスコントロール膜150に注入する。デジタル回路領域のPMOSトランジスタを除くあらゆる領域でストレスコントロール膜150はストレス解除膜またはストレス緩和膜152に変換され、デジタル回路領域のPMOSトランジスタのチャネル104bだけに圧縮応力が印加される状態が残る。
【選択図】図8
Description
102 STI
104a、104b、104c、104d トランジスタのチャンネル
110 ゲート絶縁膜パターン
120 導電性ゲートパターン
122 低濃度ソース/ドレーン領域
124 側壁スペーサ
126 高濃度ソース/ドレーン領域
128 ソース/ドレーン領域
130 シリサイドパターン
150 ストレスコントロール膜
152 ストレス解除膜またはストレス緩和膜
160 フォトレジストマスク
162 Ge、Si、As、In、Sbなどのイオンストレスコトロール膜
Claims (4)
- 回路の第1領域に第1導電型の第1MOS素子を形成する段階と、
前記回路の第2領域に前記第1MOS素子と同一導電型である第1導電型の第2MOS素子を形成する段階と、
前記第1MOS素子及び第2MOS素子のうち前記第1MOS素子のチャンネルにストレスを印加する段階と、を含み、
前記第1MOS素子のチャンネルにのみストレスを印加する段階前に、
前記第1及び第2MOS素子に近接して第1相のシリサイドを形成するために第1熱処理を行う段階と、
前記第1及び第2MOS素子と前記第1相のシリサイド上にキャッピング層を形成する段階をさらに含む
ことを特徴とする回路製造方法。 - 前記第1MOS素子及び第1相のシリサイド上で前記キャッピング層の一部を除去する段階をさらに含む
ことを特徴とする請求項1に記載の回路製造方法。 - 前記第1MOS素子のチャンネルにストレスを印加する前に前記第1MOS素子と前記第2相のシリサイドを露出させるように前記キャッピング層の一部を除去し、
前記第1MOS素子のチャンネルにストレスを印加する段階は、前記第2MOS素子が前記キャッピング層で覆われている状態で前記第1相のシリサイドを第2相のシリサイドに転換させるために第2熱処理を行う段階をさらに含む
ことを特徴とする請求項2に記載の回路製造方法。 - 回路の第1領域に形成された第1導電型の第1MOS素子と、
前記回路の第2領域に形成された前記第1MOS素子と同一導電型である第1導電型の第2MOS素子と、を含み、
前記第1MOS素子のチャンネルにはストレスが印加されており、前記第2MOS素子にはストレスが印加されておらず、
前記第1MOS素子のチャンネルにストレスを印加するために前記第1MOS素子のソース/ドレーン領域上に形成された第2相のシリサイドをさらに含む
ことを特徴とする回路。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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KR1020040021569A KR101025761B1 (ko) | 2004-03-30 | 2004-03-30 | 디지탈 회로 및 아날로그 회로를 가지는 반도체 집적회로및 그 제조 방법 |
KR2004-021569 | 2004-03-30 | ||
US11/067,836 US7545002B2 (en) | 2004-03-30 | 2005-02-28 | Low noise and high performance LSI device, layout and manufacturing method |
US11/067,836 | 2005-02-28 |
Related Parent Applications (1)
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JP2005099739A Division JP2005286341A (ja) | 2004-03-30 | 2005-03-30 | 低ノイズ及び高性能のlsi素子、レイアウト及びその製造方法 |
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JP2013030780A true JP2013030780A (ja) | 2013-02-07 |
JP5604483B2 JP5604483B2 (ja) | 2014-10-08 |
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JP (1) | JP5604483B2 (ja) |
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JP2005286341A (ja) * | 2004-03-30 | 2005-10-13 | Samsung Electronics Co Ltd | 低ノイズ及び高性能のlsi素子、レイアウト及びその製造方法 |
US7238990B2 (en) * | 2005-04-06 | 2007-07-03 | Freescale Semiconductor, Inc. | Interlayer dielectric under stress for an integrated circuit |
KR20070000814A (ko) * | 2005-06-28 | 2007-01-03 | 매그나칩 반도체 유한회사 | 반도체 소자 제조 방법 |
US7378318B2 (en) * | 2005-08-18 | 2008-05-27 | International Business Machines Corporation | System and method for ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits |
JP4880958B2 (ja) * | 2005-09-16 | 2012-02-22 | 株式会社東芝 | 半導体装置及びその製造方法 |
DE102005046974B3 (de) * | 2005-09-30 | 2007-04-05 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erzeugen einer unterschiedlichen mechanischen Formung in unterschiedlichen Substratgebieten durch bilden einer Schicht mit verschieden modifizierter innerer Spannung und mit dem Verfahren hergestelltes Bauteil |
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US7776695B2 (en) * | 2006-01-09 | 2010-08-17 | International Business Machines Corporation | Semiconductor device structure having low and high performance devices of same conductive type on same substrate |
US7518193B2 (en) * | 2006-01-10 | 2009-04-14 | International Business Machines Corporation | SRAM array and analog FET with dual-strain layers comprising relaxed regions |
US8900980B2 (en) | 2006-01-20 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect-free SiGe source/drain formation by epitaxy-free process |
CN100466207C (zh) * | 2006-02-28 | 2009-03-04 | 联华电子股份有限公司 | 半导体晶体管元件及其制作方法 |
US7485517B2 (en) * | 2006-04-07 | 2009-02-03 | United Microelectronics Corp. | Fabricating method of semiconductor device |
US7449753B2 (en) * | 2006-04-10 | 2008-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Write margin improvement for SRAM cells with SiGe stressors |
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