JP2013016672A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2013016672A JP2013016672A JP2011148802A JP2011148802A JP2013016672A JP 2013016672 A JP2013016672 A JP 2013016672A JP 2011148802 A JP2011148802 A JP 2011148802A JP 2011148802 A JP2011148802 A JP 2011148802A JP 2013016672 A JP2013016672 A JP 2013016672A
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- insulating film
- semiconductor substrate
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- semiconductor
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Abstract
【解決手段】半導体基板1の主面に酸化膜として絶縁膜2を形成し、絶縁膜2上に窒化シリコン膜を形成してから、素子分離用の溝4aをプラズマドライエッチングにより形成し、溝4aを埋めるように酸化シリコンからなる絶縁膜6をHDP−CVD法で形成し、CMP処理により溝4aの外部の絶縁膜6を除去し、溝4a内に絶縁膜6を残す。それから、窒化シリコン膜を除去する。その後、絶縁膜2をウェットエッチングで除去して半導体基板1を露出させるが、この際、半導体基板1の主面に140ルクス以上の光を当てながら絶縁膜2をウェットエッチングする。
【選択図】図14
Description
本実施の形態の半導体装置の製造工程を図面を参照して説明する。図1は、本発明の一実施の形態である半導体装置、例えばMISFET(Metal Insulator Semiconductor Field Effect Transistor)を有する半導体装置の製造工程の一部を示す製造プロセスフロー図である。図3〜図29は、本発明の一実施の形態である半導体装置、例えばMISFETを有する半導体装置の製造工程中の要部断面図である。
次に、上記ステップS11の絶縁膜2の除去工程(ウェットエッチング工程)について、より詳細に説明する。
次に、素子分離領域形成に伴う欠陥発生について説明する。
そこで、本実施の形態では、ステップS11の絶縁膜2の除去(ウェットエッチング)工程において、照明装置36からの光44を半導体ウエハSWに当てる(照射する)ようにしている。すなわち、ステップS11では、半導体ウエハSWに照明装置36からの光44を当てながら(照射しながら)、絶縁膜2をウェットエッチングする。光44を半導体ウエハSWに当てるのは、光電効果によりSi基板(半導体基板1に対応するSi基板領域)で電荷(ここでは主として電子)を発生させてこれをSi基板側から絶縁膜2側に供給し、絶縁膜2に既に蓄えられていた電荷(主として正孔が蓄えられている)を中和させる(電子と正孔とを結合させて消滅させる)ためである。
E=hν=h×c/λ ・・・(式1)
で表される。式1中のEはエネルギー、hはプランク定数、νは振動数、cは光の速さ、λは波長である。式1より、1.1eV以上のエネルギーを与えるには、1127nm以下の波長の光が必要であることが分かる。このため、ステップS11(絶縁膜2のウェットエッチング工程)において半導体ウエハSWに照射する光44は、1127nm以下の波長の光とすればよい。
また、本実施の形態では、素子分離領域4形成に伴うピット51の発生を抑制または防止するために、ステップS11の絶縁膜2のウェットエッチング工程で半導体ウエハSWに光44を照射している。しかしながら、ステップS11(絶縁膜2除去工程)よりも後において、半導体基板1(半導体ウエハSW)の主面に絶縁膜と該絶縁膜上のレジスト層(エッチングマスクとして機能するフォトレジスト層)とが形成された状態で前記絶縁膜のウェットエッチングを行って半導体基板1を露出させる際には、半導体基板1(半導体ウエハSW)の主面に100ルクス以上の光が照射されないようにする。これは、レジスト層(フォトレジスト層)は、光が照射されると変質し(例えば硬くなり)、後で除去しにくくなるためである。
1A 高耐圧MIS領域
1B 低高耐圧MIS領域
2 絶縁膜
3 絶縁膜
4 素子分離領域
4a 溝
5 絶縁膜
6 絶縁膜
11 絶縁膜
12 絶縁膜
13 導電体膜
22 絶縁膜
23 コンタクトホール
24 プラグ
25 絶縁膜
31 半導体製造装置
32 搬送室
33 エッチング用チャンバ
34 ロードポート
35 搬送用ロボット
36 照明装置
41 回転ステージ
42 ノズル
43 エッチング液
51 ピット
102 酸化膜
104a 溝
105 絶縁膜
106 絶縁膜
EX エクステンション領域
GE,GE1,GE2 ゲート電極
M1 配線
PR1,PR2,PR3,PR4 フォトレジストパターン
Q1,Q2 MISFET
SD ソース・ドレイン領域
SP サイドウォールスペーサ
SW 半導体ウエハ
Claims (17)
- (a)半導体基板を準備する工程、
(b)前記半導体基板の主面に第1絶縁膜を形成する工程、
(c)前記第1絶縁膜および前記半導体基板をプラズマドライエッチングすることにより、前記第1絶縁膜および前記半導体基板に素子分離用の溝を形成する工程、
(d)前記溝を埋めるように、前記半導体基板の主面上に第2絶縁膜を形成する工程、
(e)CMP処理により前記溝の外部の前記第2絶縁膜を除去し、前記溝内に前記第2絶縁膜を残す工程、
(f)前記第1絶縁膜をウェットエッチングで除去して前記半導体基板を露出させる工程、
を有し、
前記(f)工程では、前記半導体基板の主面の少なくとも一部に140ルクス以上の光を当てながら前記第1絶縁膜をウェットエッチングすることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程では、回転する前記半導体基板の主面の少なくとも一部に140ルクス以上の光を当てながら前記第1絶縁膜をウェットエッチングすることを特徴とする半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記(f)工程では、回転する前記半導体基板の主面に前記第1絶縁膜をエッチングするためのエッチング液を供給して、前記第1絶縁膜をウェットエッチングすることを特徴とする半導体装置の製造方法。 - 請求項3記載の半導体装置の製造方法において、
前記(f)工程では、前記半導体基板の主面のいずれの領域も、前記第1絶縁膜をウェットエッチングしている間に140ルクス以上の光が照射されている期間を有することを特徴とする半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
前記第1絶縁膜は、酸化膜であることを特徴とする半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法において、
前記(b)工程では、熱酸化により前記第1絶縁膜を形成することを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(b)工程後で、前記(c)工程前に
(b1)前記第1絶縁膜上に第3絶縁膜を形成する工程、
を更に有し、
前記(c)工程では、前記第3絶縁膜、前記第1絶縁膜および前記半導体基板をプラズマドライエッチングすることにより、前記第3絶縁膜、前記第1絶縁膜および前記半導体基板に素子分離用の溝を形成し、
前記(e)工程後で、前記(f)工程前に、
(e1)前記第3絶縁膜を除去して前記第1絶縁膜を露出させる工程、
を更に有することを特徴とする半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記第3絶縁膜は、窒化シリコン膜であることを特徴とする半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記(d)工程では、プラズマCVD法により前記第2絶縁膜を形成することを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記(d)工程では、高密度プラズマCVD法により前記第2絶縁膜を形成することを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記第2絶縁膜は、酸化シリコン膜であることを特徴とする半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記(f)工程では、前記半導体基板の主面上にレジスト層が形成されていない状態で、前記第1絶縁膜をウェットエッチングすることを特徴とする半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記(f)工程の後において、前記半導体基板の主面に絶縁膜と前記絶縁膜上のレジスト層とが形成された状態で前記絶縁膜のウェットエッチングを行って前記半導体基板を露出させる際には、前記半導体基板の主面に100ルクス以上の光が照射されないようにすることを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記絶縁膜は、MISFETのゲート絶縁膜用の絶縁膜であることを特徴とする半導体装置の製造方法。 - (a)半導体基板を準備する工程、
(b)前記半導体基板の主面に第1絶縁膜を形成する工程、
(c)前記第1絶縁膜および前記半導体基板をプラズマドライエッチングすることにより、前記第1絶縁膜および前記半導体基板に素子分離用の溝を形成する工程、
(d)前記溝を埋めるように、前記半導体基板の主面上に第2絶縁膜を形成する工程、
(e)CMP処理により前記溝の外部の前記第2絶縁膜を除去し、前記溝内に前記第2絶縁膜を残す工程、
(f)前記第1絶縁膜をウェットエッチングで除去して前記半導体基板を露出させる工程、
を有し、
前記(f)工程では、前記半導体基板の主面に光を当てながら前記第1絶縁膜をウェットエッチングし、
前記(f)工程の後において、前記半導体基板の主面に絶縁膜と前記絶縁膜上のレジスト層とが形成された状態で前記絶縁膜のウェットエッチングを行って前記半導体基板を露出させる際には、前記半導体基板の主面の照度が、前記(f)工程における前記半導体基板の主面の照度よりも低くなるようにすることを特徴とする半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、
前記(f)工程では、前記半導体基板の主面上にレジスト層が形成されていない状態で、前記第1絶縁膜をウェットエッチングすることを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記絶縁膜は、MISFETのゲート絶縁膜用の絶縁膜であることを特徴とする半導体装置の製造方法。
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WO2016152394A1 (ja) * | 2015-03-26 | 2016-09-29 | 株式会社Screenホールディングス | 基板処理装置および基板処理方法 |
JP2016184701A (ja) * | 2015-03-26 | 2016-10-20 | 株式会社Screenホールディングス | 基板処理装置および基板処理方法 |
KR20170122247A (ko) * | 2015-03-26 | 2017-11-03 | 가부시키가이샤 스크린 홀딩스 | 기판 처리 장치 및 기판 처리 방법 |
KR101980994B1 (ko) | 2015-03-26 | 2019-05-21 | 가부시키가이샤 스크린 홀딩스 | 기판 처리 장치 및 기판 처리 방법 |
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CN102867739A (zh) | 2013-01-09 |
US20150357231A1 (en) | 2015-12-10 |
TWI553724B (zh) | 2016-10-11 |
US9142443B2 (en) | 2015-09-22 |
TW201637090A (zh) | 2016-10-16 |
TW201318054A (zh) | 2013-05-01 |
JP5859758B2 (ja) | 2016-02-16 |
US20130011996A1 (en) | 2013-01-10 |
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