CN103871899B - 一种finfet结构的制备方法 - Google Patents

一种finfet结构的制备方法 Download PDF

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CN103871899B
CN103871899B CN201410060243.4A CN201410060243A CN103871899B CN 103871899 B CN103871899 B CN 103871899B CN 201410060243 A CN201410060243 A CN 201410060243A CN 103871899 B CN103871899 B CN 103871899B
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silicon nitride
oxide
finfet
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fin structure
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CN103871899A (zh
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丁弋
陈锟
朱也方
李芳�
王从刚
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Shanghai Huali Microelectronics Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means

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Abstract

本发明提供一种FINFET结构的制备方法,包括:研磨掉氮化硅2上的氧化硅1;通过低选择比研磨液继续研磨一定量的氧化硅1和氮化硅2,以减薄氮化硅2的厚度;湿法刻蚀去除氮化硅;湿法刻蚀去除部分氧化硅1,形成FinFET结构。本发明的技术方案简便易行,利用两次CMP制程,减薄氮化硅的厚度,增加氮化硅的宽度,即增加氮化硅与药剂的接触面积,有利于湿法对氮化硅的去除,最终达到氮化硅的完全去除,避免了氮化硅去除不完全的后果。

Description

一种FINFET结构的制备方法
技术领域
本发明涉及半导体制造领域,尤其涉及一种FINFET结构的制备方法。
背景技术
FinFET称为鳍式场效晶体管(Fin Field-Effect Transistor;FinFET)是一种新的互补式金氧半导体(CMOS)晶体管。Fin是鱼鳍的意思,FinFET命名根据晶体管的形状与鱼鳍的相似性。
目前,现有技术通过CMP形成FinFET,在第一步常规STI(shallow trenchisolation浅沟道隔离)-CMP完成以后,第二步利用dry etch(干法刻蚀)刻蚀掉一定量的oxide(氧化物),第三步利用H3PO4去除有源区上的Nitride(氮化物),第四部利用wet etch(湿法刻蚀)刻蚀掉一定量的oxide,最终形成FinFET结构。
这种集成方案在Nitride remove(氮化物去除)时,由于FinFET结构有源区CD很小,H3PO4液很难进入狭小空间,可能导致Nitride残留,去除不完全;并且在第四步利用湿法刻蚀去除一定量的STI区域的Oxide时,也会对有源区上的Oxide造成侵蚀。这种缺陷在技术节点达到20nm及以下是无法容忍的。
专利CN101097956公开了一种FINFET结构及FINFET结构的制作方法。该方法包括:在硅基片顶表面形成硅鳍片;在鳍片的相对侧壁上形成栅极电介质;在鳍片的沟道区域上形成栅电极,栅电极与位于鳍片的相对侧壁上的栅极电介质层形成直接的物理接触;在鳍片内沟道区域的第一面上形成第一源/漏区,在鳍片内沟道区域的第二面上形成第二源/漏区;从至少部分第一和第二源/漏区下方去除部分基片以形成空隙;用电介质材料填充空隙;本结构还包括FINFET的硅体与基片之间的体接触。但该专利存在氮化物去除缺陷问题。
专利CN103383961A公开了一种FinFET结构及制造方法,采用呈三棱柱状的鳍形沟道区替代长方体状的鳍形沟道区,其凸出的两面形成相对的晶面晶向结构,减少载流子散射效应,提高电荷存储能力,受到栅极的控制时更容易构造出鳍形沟道区全耗尽结构,彻底切断沟道的导电通路,从而提高FinFET器件的驱动电流,适用于更小尺寸和更高驱动电流的FinFET器件的制造。但该专利任然存在氮化物去除缺陷问题。
发明内容
鉴于上述问题,本发明提供一种FINFET结构的制备方法。
本发明解决技术问题所采用的技术方案为:
一种FINFET结构的制备方法,其中,包括以下步骤:
步骤1,提供待研磨晶圆,所述晶圆的STI区域由底部至顶部依次设有缓冲垫氧化层、氮化硅和氧化物,所述晶圆的其他区域由底部至顶部依次设有缓冲垫氧化层和氧化物层,位于STI区域的缓冲垫氧化层的顶部高于其他区域中的缓冲垫氧化层的顶部;
步骤2,研磨掉氮化硅上的氧化硅;
步骤3,继续研磨一定量的氧化硅和氮化硅;
步骤4,湿法刻蚀去除氮化硅;
步骤5,湿法刻蚀去除部分氧化硅,形成FinFET结构。
所述的FINFET结构的制备方法,其中,所述步骤2包括:
步骤2.1,采用固定研磨时间对氧化硅研磨;
步骤2.2,采用高选择比研磨液对氧化硅进行研磨。
所述的FINFET结构的制备方法,其中,所述步骤3中通过低选择比研磨液对氧化硅和氮化硅进行研磨,以减薄氮化硅的厚度。
所述的FINFET结构的制备方法,其中,所述步骤3中的继续研磨氧化硅和氮化硅的量为
所述的FINFET结构的制备方法,其中,所述步骤4中通过磷酸去除氮化硅。
所述的FINFET结构的制备方法,其中,所述步骤1中的缓冲垫氧化层通过原子层沉积法形成。
所述的应用于FINFET结构的化学机械研磨方法,其中,所述步骤1中的缓冲垫氧化层通过等离子体增强化学气相沉积法形成。
上述技术方案具有如下优点或有益效果:
本发明的方法简便易行,利用两次CMP制程,减薄氮化硅的厚度,增加氮化硅的宽度,即增加氮化硅与药剂的接触面积,有利于湿法对氮化硅的去除,最终达到氮化硅的完全去除,避免了氮化硅去除不完全的后果。
附图说明
参考所附附图,以更加充分的描述本发明的实施例。然而,所附附图仅用于说明和阐述,并不构成对本发明范围的限制。
图1是本发明实施例研磨去除氮化硅上氧化硅的结构示意图;
图2是本发明实施例继续研磨氮化硅和氧化硅的结构示意图;
图3是本发明实施例去除氮化硅的结构示意图;
图4是本发明实施例的FINFET结构示意图。
具体实施方式
本发明提供一种FINFET结构的制备方法,在常规第一步CMP完成以后,进一步利用低选择比的研磨液研磨,以减薄氮化硅的厚度,最终使得氮化硅达到可以接受的厚度,满足后续湿法去除的要求。这种方法和现有技术相比,减少了氮化硅的厚度,研磨一段时间后,暴露出来的氮化硅宽度也会增加,这些将有利于湿法的清洗。并且由于低选择比的研磨液去除氧化硅的速率大于氮化硅的速率,所以研磨一段时间后,氮化硅呈现凸起状态,这样更有利于湿法的去除,最终达到氮化硅完全去除的效果。
下面结合附图对本发明方法进行详细说明。
本发明实施例的一种FINFET结构的制备方法,其中,包括以下步骤:
步骤1,提供待研磨晶圆,具有氧化硅1、氮化硅2、缓冲垫氧化层3;
如图1中所示,步骤2,研磨掉氮化硅2上的氧化硅1;
如图2中所示,步骤3,通过低选择比研磨液继续研磨一定量的氧化硅1和氮化硅2,以减薄氮化硅2的厚度;
如图3中所示,步骤4,湿法刻蚀去除氮化硅;
如图4中所示,步骤5,湿法刻蚀去除部分氧化硅1,形成FinFET结构。
本发明实施例的在常规第一步CMP完成以后,进一步利用低选择比的研磨液研磨,以减薄氮化硅的厚度,最终使得氮化硅达到可以接受的厚度,接着利用一定温度和用量的磷酸对氮化硅进行去除,最后利用湿法对氧化硅进行刻蚀,最终形成FinFET结构。其利用两次CMP制程,减薄氮化硅的厚度,增加氮化硅的宽度,即增加氮化硅与药剂的接触面积,有利于湿法对氮化硅的去除,最终达到氮化硅的完全去除,避免了氮化硅去除不完全的后果。
对于本领域的技术人员而言,阅读上述说明后,各种变化和修正无疑将显而易见。因此,所附的权利要求书应看作是涵盖本发明的真实意图和范围的全部变化和修正。在权利要求书范围内任何和所有等价的范围与内容,都应认为仍属本发明的意图和范围内。

Claims (7)

1.一种FINFET的鳍状结构的制备方法,其特征在于,包括以下步骤:
步骤1,提供待研磨晶圆,所述晶圆的STI区域由底部至顶部依次设有缓冲垫氧化层、氮化硅和氧化物,所述晶圆的其他区域由底部至顶部依次设有缓冲垫氧化层和氧化物层,位于STI区域的缓冲垫氧化层的顶部高于其他区域中的缓冲垫氧化层的顶部;
步骤2,研磨掉氮化硅上的氧化物;
步骤3,继续研磨一定量的氧化物层和氮化硅;
步骤4,湿法刻蚀去除氮化硅;
步骤5,湿法刻蚀去除部分氧化物层,使位于STI区域的缓冲垫氧化层高于位于晶圆的其他区域的剩余的氧化物层,以形成鳍状结构。
2.如权利要求1所述的FINFET的鳍状结构的制备方法,其特征在于,所述步骤2包括:
步骤2.1,采用固定研磨时间对氧化物研磨;
步骤2.2,采用高选择比研磨液对氧化物进行研磨。
3.如权利要求2所述的FINFET的鳍状结构的制备方法,其特征在于,所述步骤3中通过低选择比研磨液对氧化物层和氮化硅进行研磨,以减薄氮化硅的厚度。
4.如权利要求3所述的FINFET的鳍状结构的制备方法,其特征在于,所述步骤3中的继续研磨氧化物层和氮化硅的量为
5.如权利要求4所述的FINFET的鳍状结构的制备方法,其特征在于,所述步骤4中通过磷酸去除氮化硅。
6.如权利要求1中所述的FINFET的鳍状结构的制备方法,其特征在于,所述步骤1中的缓冲垫氧化层通过原子层沉积法形成。
7.如权利要求1所述的FINFET的鳍状结构的制备方法,其特征在于,所述步骤1中的缓冲垫氧化层通过等离子体增强化学气相沉积法形成。
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US9012286B2 (en) * 2012-04-12 2015-04-21 Globalfoundries Inc. Methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices
US8932936B2 (en) * 2012-04-17 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a FinFET device
US20130302954A1 (en) * 2012-05-10 2013-11-14 Globalfoundries Inc. Methods of forming fins for a finfet device without performing a cmp process

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CN102867739A (zh) * 2011-07-05 2013-01-09 瑞萨电子株式会社 制造半导体器件的方法
CN103021851A (zh) * 2011-09-21 2013-04-03 中芯国际集成电路制造(上海)有限公司 一种多栅极场效应晶体管的制作方法

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