TW201618307A - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TW201618307A
TW201618307A TW104100109A TW104100109A TW201618307A TW 201618307 A TW201618307 A TW 201618307A TW 104100109 A TW104100109 A TW 104100109A TW 104100109 A TW104100109 A TW 104100109A TW 201618307 A TW201618307 A TW 201618307A
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廖偉明
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南亞科技股份有限公司
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Abstract

一種半導體元件，具有頸部鰭結構。半導體元件包括一基底；複數個鰭結構，設於該基底上，其中，各該鰭結構具有一下部分和一頸部上部分；以及一絕緣體，設置在該複數個鰭結構之間，與該鰭結構的下部分齊平。

Description

半導體元件及其製造方法
本發明涉及一種半導體元件及其製造方法，更具體地，本發明涉及一具有頸部鰭結構的凹陷通道陣列電晶體(RCAT)及其製造方法。
隨著半導體記憶體元件朝更高度集成，記憶胞的尺寸逐漸縮小。目前研究重點在於形成具有所要單元電容的記憶元件和/或針對更小的記憶元件改善其單元電晶體的特性。當記憶胞的尺寸微縮時，即需要更小的單元電晶體。為實現具有期望特性的單元電晶體，已有提出控制擴散層中摻質濃度的方法，但是當通道長度微縮，在各種熱處理工序中控制電晶體的擴散層深度變得越來越困難。若有效通道長度和/或閾值電壓降低，將發生短通道效應。短通道效應將導致單元電晶體在操作時發生問題。
為了解決上述問題，目前已發展出凹陷通道陣列電晶體(RCAT)，其中一凹槽形成在基底的表面，而將晶體管的閘極形成在凹槽。因為閘極被設置在基底的凹槽內，源極和汲極之間的距離被拉長，使得有效通道長度增加，從而改善了短通道效應。
然而，隨著記憶體進一步縮小，相鄰字線之間的效應與干擾成為問題，與被編程記憶胞共用位元線的另一記憶胞，會受到導通電壓干擾。這種現象也被稱為字線干擾(WL disturb)，會影響記憶體的保留時間(retention time)。
一種解決字線干擾的常規方法是用於形成非對稱接面(較深Dgt接面)的佈植控制，但這種方法會降低記憶胞側接面控制的製程餘裕度。另 一種方法是較深鰭結構，但形成較深鰭結構的過程容易損壞陣列底部和改變性能。
由此可知，有必要在本領域中提供一種解決方案，以最小化在Vpgm電壓範圍內相鄰字線的干擾。
為了減輕相鄰字線干擾問題，本發明提供半導體結構與頸部鰭結構。本發明頸部鞍鰭(兩側窄且凹)，結合較重摻雜修正，顯示顯著改善相鄰字線干擾問題，較小的Vt/SVt，更高的Ids，和在相同SVt有更好的Ids/Ioff。
本發明的一個目的是提供一種半導體元件，具有頸部鰭結構。半導體元件包括一基底；複數個鰭結構，設於該基底上，其中，各該鰭結構具有一下部分和一頸部上部分；以及一絕緣體，設置在該複數個鰭結構之間，與該鰭結構的下部分齊平。
本發明另提供一種製作半導體元件的方法，包含：於一基底上形成複數個鰭結構；形成一絕緣體，設置在該複數個鰭結構之間，與該鰭結構齊平；僅於該複數個鰭結構的頂面形成一光阻；去除部分該絕緣體，使該鰭結構的上部分突出於該絕緣體；以及在該鰭結構的頂面設有該光阻下，蝕刻該突出的該鰭結構的上部分，藉以形成該鰭結構的一頸部上部分。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
100‧‧‧基底
101‧‧‧鰭結構
101a‧‧‧上部分
101b‧‧‧下部分
103‧‧‧溝槽
105‧‧‧絕緣體
107‧‧‧圖案化光阻
109‧‧‧閘極絕緣膜
111‧‧‧導電層
第1-6圖例示性的依據本發明實施例以剖面視圖繪示出形成具有頸部鰭結構的半導體元件的流程。
在本發明的以下詳細描述中，參考了形成本文的一部分的圖式，其例示可實踐本發明的具體實施例。這些實施例被足夠詳細地描述以使本領域的技術人員能夠實踐本發明。其它實施例可以被利用，並且可以做出結構，邏輯和電性上的變化而不脫離本發明的範圍。下面的詳細說明，因此，不被視為具有限制意義，並且本發明的範圍是由所附權利要求而定。
在進一步的描述優選實施例之前，以下先針對全文中使用的特定用語進行說明。
用語“蝕刻”在本文中通常用來描述圖案化材料的製程，使得在蝕刻完成後的材料的至少一部分能被留下。例如，應該理解的是，蝕刻矽的方法包括在矽上面圖案化一掩模層(例如，光阻或硬掩模)，然後從不被掩模層保護的區域。因此，在蝕刻過程完成，由掩模保護的區域的矽會留下。然而，在另一實例中，刻蝕也可以指不使用掩模的方法，但在蝕刻過程完成後仍留下至少一部分的材料。上面的說明用來從區分“刻蝕”及“去除”。當“蝕刻”一材料，該材料的至少一部分在處理結束後後被保留。與此相反，“去除”材料時，基本上所有的材料是在過程中除去。然而，在一些實施例中，“去除”被認為是一個廣義的用語，可以包括刻蝕。
在下文的描述中，將提及基底上製造有場效元件的各區域。但是應當理解的是，這些區域可能存在在基底上的任意位置，此外，該區域可能不是相互排斥的。即，在一些實施方案中，一個或多個區域部分可能重疊。雖然多達三個不同的區域在本文中描述，但是應該理解的是，任何數量的區域可存在於基底上，並可以指定具有特定類型的元件或材料的區域。在一般情況下，該區域被用於方便描述，包括類似的元件，並且不應限制本描述的實施例的範圍或精神的基底區域。
用用語“形成”、“沉積”或術語“設置”在下文中係用於描述施加一層材料於基底的行為。這樣的用語是為了描述任何可能的層形成技術，包括但不限於，熱生長，濺射，蒸發，化學氣相沉積，磊晶生長，電鍍 等。根據各種實施例，例如，沉積可以任何適當的公知方法進行。例如，沉積可以包括任何生長、鍍層，或轉移材料到基底上的過程。一些公知的技術包括物理氣相沉積(PVD)、化學氣相沉積(CVD)、電化學沉積(ECD)、分子束外延(MBE)、原子層沉積(ALD)、電漿增強CVD(PECVD)等。
全文中所描述的“基底”，最常見的應該是矽基底。然而，基底也可以是任何半導體材料，例如鍺、砷化鎵、磷化銦等。在其它實施例的，基底可以是不導電的，例如玻璃或藍寶石晶圓。
在本發明的例示實施例中，半導體元件可作為動態隨機存取記憶體(DRAM)的一部分。半導體元件包括半導體基底1，具有記憶胞陣列區，其內設有多個存儲器單元(未示出)。由於本發明主要著重在鰭狀結構的新穎頸部輪廓，詳細過程的說明將參照橫截面視圖，而不是平面圖，並且每個所示部分的大小，厚度等，可能不同於實際半導體元件的各部分。
請參考第1圖，首先提供一基底100，做為形成鰭狀結構的基礎。基底100可以包括，但不限於，矽基底，含矽基底，矽上氮化鎵(GaN-on-silicon或III-V族的其他材料)，矽上石墨烯(graphene-on-silicon)基底，或矽上絕緣體(SOI)襯底，並依此類推。
在基底100上形成多個鰭結構101，例如連接字線的鞍鰭結構。鰭結構101可以通過以下方法形成：(1)在基底100上形成掩模層(未示出)，掩模層可包括氮化矽(SiN)膜、無定形碳(α-C)膜、氮氧化矽(SiON)膜、氧化矽(SiO)膜，或抗反射(BARC)膜；(2)形成一個光阻(PR)膜覆蓋在掩模層上，光阻膜透過微影製程圖案化，其對應於主動區的形狀；(3)以圖案化的光阻膜為擋罩通過非等向性蝕刻圖案化該掩模層，使光阻膜的圖案轉印到掩模層；(4)以圖案化的掩模層為擋罩通過非等向性蝕刻工藝圖案化半導體基底100。掩模層的圖案被轉印到半導體基底100的表面上，並且形成多個從所述基底100延伸的鰭結構101，其間形成隔離溝槽103；和(5)通過濕蝕刻工藝，例如用加熱的磷酸(H3PO4)，除去圖案化的掩模層。 由於上述形成常規鰭結構的方法是公知的，為了簡化說明，在本說明書中省略了進一步詳細的描述和相關的說明。
現在請參考第2圖。形成鰭結構101及定義了隔離區和主動區之後，在鰭結構101之間形成與鰭結構101齊平的絕緣體105。在此實施例，絕緣體105可以先在半導體基底100整個表面沉積氧化矽膜、氮化矽膜(未示出)或以上兩者，可利用高密度電漿化學氣相沉積(HDP-CVD)工藝或低壓化學氣相沉積(LP-CVD)工藝。氮化矽膜或氮化矽膜填滿鰭結構101之間的隔離溝槽103的並覆蓋鰭結構101。然後，對氧化矽(氮化矽)膜的表面進行拋光，通過化學機械研磨(CMP)，直到鰭結構101的頂面被暴露。在一個實施例中，絕緣體105可以是淺溝絕緣(STI)。鰭結構101和絕緣體105定義出隔離區和主動區，其可平行交替地佈置且在第一方向延伸。
現在請參考第3圖。在形成絕緣體105，並在基底100上獲得一平坦表面後，在基底100上形成一圖案化光阻107。如第3圖所示，圖案化光阻107恰好覆蓋住露出的鰭結構101。在本發明的實施例中，圖案化光阻107可以類似於用於圖案化硬掩模，並定義所述鰭結構101(即主動區)的光阻，如在第1圖中所示的步驟。應當注意的是，圖案化光阻107的寬度應至少比鰭結構101的寬度大，以覆蓋整個鰭結構101。如圖3所示，圖案化光阻107形成後，只有絕緣體105被暴露出來。
現在請參考第4圖。於鰭結構101上覆蓋圖案化光阻107後，進行回蝕刻以去除部分的絕緣體105。回蝕刻降低了絕緣體105一部分厚度，使得鰭結構101從絕緣體105中突出來。若絕緣體105是氧化矽膜，通過非等向性蝕刻或者氫氟酸(HF)濕蝕刻，絕緣體105可被選擇性地被除去(縮減)。或者，當絕緣體105是氮化矽膜，通過濕蝕刻，如加熱的磷酸，絕緣體105可被選擇性地被除去(縮減)。此時，絕緣體105具有預定垂直厚度保持在記憶胞陣列區中的溝槽103的底部。在本實施例中，鰭結構101的突出部被稱為鰭結構101的上部分101a，而鰭結構101的未顯露部分被稱為的鰭結 構101的下部分101b。請注意，剩餘的絕緣體105與鰭結構101的下部分101b平齊。
現在請參考第5圖。在降低絕緣體105的厚度，並形成一個突出的鰭結構101上部分101a之後，進行乾蝕刻工藝來蝕刻的鰭結構101暴露出的上部分101a。不同於常用的乾蝕刻工藝，上述乾蝕刻工藝係在鰭結構101上覆蓋有圖案化光阻107下進行。上述乾蝕刻工藝從鰭結構101的側壁進行而不蝕刻頂表面。另外，在本實施例中，鰭結構101的暴露側壁的中部會受到比側壁的拐角更多蝕刻反應。因此，可以注意到，在鰭結構101的中間部分的寬度縮減將超過的拐角部，從而形成一個突出鰭結構101的頸上部。上述橫向蝕刻工藝還提供了減少鰭結構101的寬度的效果。
形成突出的頸部鰭結構101之後，請參照第6圖，下面的過程可以是標準RCAT製程，例如：(1)利用剝離製程除去圖案化光阻107；(2)通過熱氧化工藝，如原位蒸汽產生(ISSG)製程，於鰭結構101和基底100上形成一共形的閘極絕緣膜109；及(3)於鰭結構101和基底100上形成一導電層111。請注意，在本實施例中，導電層111的一部分埋入在所述凹進的閘極溝槽103並跨在整個鰭結構101上，由此形成一個鞍鰭結構通道。所述半導體元件的通道結構可以實現更長的閘極通道長度和防止短通道效應。在本實施例中，導電層111可以用作在DRAM結構中的選擇電晶體的閘電極(即，字線)。導電層111可以與佈置在週邊區中的接觸墊進一步連接。
其他通常RCAT製程，例如過程，形成汲極區、源極區，或虛設字線，在為了簡化，在本實施例中省略，以不混淆本發明的精神和範圍。很明顯的是，本發明並不限定於上述實施例，並且可以進行修改和改變而不脫離本發明的範圍和精神。例如，本發明並不限於具有鞍鰭形通道結構的半導體裝置，本發明也適用於具有三維通道結構的各種半導體裝置，例如，凹陷通道結構和鰭狀通道結構。
本發明提供的上述方法可以製造具有頸鞍鰭的半導體元件。所述 頸部內凹側壁輪廓不僅減輕了常規相鄰字線干擾的問題，而且還提供了較通常RCAT製程所能形成的更窄寬度的鰭結構。結合較重摻雜修正，頸部鞍鰭能夠進一步顯示在電氣性能上顯著的改善，如較小的Vt/SVt，更高的Ids和在相同的SVt有更好的Ids/Ioff。
本發明還提供了一種半導體元件，包括但不限於，一基底100，多個鰭結構101，設於基底100上，其中，每個鰭結構101具有下部分101b和一頸部上部分101a，以及設置在鰭結構101之間的絕緣體105，與鰭結構101的下部分101b齊平。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100‧‧‧基底
101‧‧‧鰭結構
101a‧‧‧上部分
101b‧‧‧下部分
103‧‧‧溝槽
105‧‧‧絕緣體
109‧‧‧閘極絕緣膜
111‧‧‧導電層

Claims (7)

  1. 一種半導體元件，包含：一基底；複數個鰭結構，設於該基底上，其中，各該鰭結構具有一下部分和一頸部上部分；以及一絕緣體，設置在該複數個鰭結構之間，與該鰭結構的下部分齊平。
  2. 如申請專利範圍第1項所述的半導體元件，其中另包含一閘極絕緣膜，共形的設置在該鰭結構的頸部上部分以及該絕緣體上。
  3. 如申請專利範圍第1項所述的半導體元件，其中另包含有字線，跨坐於該鰭結構的頸部上部分。
  4. 一種製作半導體元件的方法，包含：於一基底上形成複數個鰭結構；形成一絕緣體，設置在該複數個鰭結構之間，與該鰭結構齊平；僅於該複數個鰭結構的頂面形成一光阻；去除部分該絕緣體，使該鰭結構的上部分突出於該絕緣體；以及在該鰭結構的頂面設有該光阻下，蝕刻該突出的該鰭結構的上部分，藉以形成該鰭結構的一頸部上部分。
  5. 如申請專利範圍第4項所述的製作半導體元件的方法，其中另包含：在形成該鰭結構的該頸部上部分之後，去除該光阻。
  6. 如申請專利範圍第4項所述的製作半導體元件的方法，其中另包含：在該鰭結構的該頸部上部分以及該絕緣體上，形成一共形的閘極絕緣膜。
  7. 如申請專利範圍第4項所述的製作半導體元件的方法，其中另包含：形成一字線，跨坐於該鰭結構的該頸部上部分。
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