JP2012506628A - 基板上にはんだ堆積物を形成する方法 - Google Patents
基板上にはんだ堆積物を形成する方法 Download PDFInfo
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- JP2012506628A JP2012506628A JP2011532577A JP2011532577A JP2012506628A JP 2012506628 A JP2012506628 A JP 2012506628A JP 2011532577 A JP2011532577 A JP 2011532577A JP 2011532577 A JP2011532577 A JP 2011532577A JP 2012506628 A JP2012506628 A JP 2012506628A
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Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/30—Electroplating: Baths therefor from solutions of tin
- C25D3/32—Electroplating: Baths therefor from solutions of tin characterised by the organic bath constituents used
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- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
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- C25D5/022—Electroplating of selected surface areas using masking means
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- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
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- C25D7/00—Electroplating characterised by the article coated
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- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Abstract
Description
1960年代初めのIBMによるフリップチップ技術の導入以来、フリップチップデバイスは、高価なセラミック基板上に搭載されてきており、その場合に、シリコンチップとセラミック基板との間の熱膨張ミスマッチはあまり決定ではない。ワイヤボンディング技術に比べて、フリップチップ技術は、より高いパッケージング密度(より低いデバイスプロファイル)及びより高い電気的性能(できる限り短いリード及びより低いインダクタンス)をより優れて提供することができる。これに基づいて、フリップチップ技術は、過去40年間、セラミック基板上の高温はんだ(コントロールド−コラップスチップコネクション、C4)を用いて工業的に実施されている。しかしながら、近年、最新の電子製品の小型化傾向のために高密度、高速及び低コストの半導体デバイスの需要が押し進められ、低コスト有機回路板(例えばプリント回路板又は基板)上に搭載され、シリコンチップと有機板構造との間の熱膨張ミスマッチにより誘導される熱応力を緩和するためのエポキシアンダーフィルを有するフリップチップデバイスが、明らかに爆発的な成長を経験している。低温フリップチップ接合及び有機ベース回路板のこの注目すべき到来は、現在の産業がフリップチップデバイスを製作するための安価な解決手段を得ることを可能にしている。
故に、本発明の対象は、スズ及びスズ合金の電気めっき法をはんだ堆積物の均一な層を基板上に生成するために採り入れることである。そのような浴は、ボイド又はディンプルを残すことなく、高アスペクト比を有するリセス構造を充填するのに適しているべきである。
本発明は、スズ又はスズ合金層を電気めっきすることによりはんだ堆積物を基板上に形成する方法を提供する。本方法は、はんだバンプを回路板上に製作するのに特に適しており、前記方法は良好なめっき均一性を有するはんだバンプを形成することができる。本方法は、以下により詳細に記載される。ここで示される図は、本方法の単なる例示に過ぎない。これらの図は、一定比に縮尺されて描かれておらず、すなわちこれらの図は前記チップパッケージ構造中の多様な層の実際の寸法又は特徴を反映しない。同番号は、明細書を通じて同要素を参照する。
欧州特許(EP)第0 616 053号明細書には、金属コーティングを非導電性基板に(無電解コーティングを用いずに)塗布する方法が記載されており、前記方法は、
a.前記基板を貴金属/IVA族金属ゾルを含んでなる活性剤と接触させて、処理された基板を得て;
b.前記処理された基板を、
(i)Cu(II)、Ag、Au又はNi可溶性金属塩又はその混合物、
(ii)第IA族金属水酸化物、
(iii)前記金属塩の金属のイオンのための、0.73〜21.95の累積生成定数log Kを有する有機材料を含んでなる錯化剤
の溶液を含んでなるpH 11超〜pH 13を有する自己促進及び自己補充する浸漬金属組成物と接触させる
ことを含んでなる。
少なくとも1つの順電流パルスの期間対少なくとも1つの逆電流パルスの期間の比は、少なくとも1:0〜1:7、好ましくは少なくとも1:0.5〜1:4及びより好ましくは少なくとも1:1〜1:2.5に調節される。
・過酸化水素、しばしばフッ化物が添加される、
・硝酸及び硝酸塩をベースとする系、硝酸塩5〜40質量%、
・HCl/塩化銅をベースとする系、塩化銅2.5mg/Lの初期濃度を有するHCl 5〜20質量%を含有する。
図1aによるコンタクトパッド構造を有するIC基板を使用する。SROは120μmであり、はんだマスク高さは25μmである。
Sn(MSA)2としてのSn2+ 45g/L、MSA(70%溶液)60mL/L、ヒドロキノン2g/L、Lugalvan BNO12 7.0g/L及びベンザルアセトン100mg/L。
順電流パルスの平均電流密度:2A/dm2;
順電流パルスの期間:20ms;
逆電流パルスの平均電流密度:0A/dm2(逆パルスなし、休止パルスのみ);
逆電流パルスの期間:4ms。
例1を繰り返すが、今度はSn(MSA)2としてSn2+ 45g/l、MSA(70%溶液)60ml/l、2−アミノ−3−ヒドロキシ−ピリジン0.5g/l、Lugalvan(登録商標) BNO12(BASF SEの製品)7.0g/l及びメタクリル酸0.5g/l及び1−ナフトアルデヒド0.05g/lからなるレベリング剤の混合物を含んでなるスズ浴を用いる。
101 導電性シード層
102 任意のバリヤー層
103 はんだマスク層
104 外層コンタクトパッド
105 非導電性基板
106 エッチレジスト
107 はんだレジスト開口部(SRO)
108 銅層
109 フォトレジスト層
110 内層コンタクトパッド
111 開口部、形成されたブラインドミクロバイア(BMV)
112 コンフォーマルコーティングされたBMV
113 スタックドBMV
114 BMV用の開口部を有する内層パッド
Claims (20)
- はんだ堆積物を基板上に形成する方法であって、次の工程:
i)少なくとも1つのコンタクト領域を含む電気回路構成を有する表面を含む基板を準備し、
ii)前記基板表面上に配置され、かつパターン形成されるはんだマスク層を形成して前記少なくとも1つのコンタクト領域を露出させ、
iii)前記はんだマスク層及び前記少なくとも1つのコンタクト領域を含む基板領域全体を、導電性層を前記基板表面上に設けるのに適した溶液と接触させ、
iv)スズ又はスズ合金を含有するはんだ堆積物層を前記導電性層上へ電気めっきし、
v)スズ又はスズ合金を含有する前記はんだ堆積物層及び前記導電性層を、前記はんだ堆積物層と前記導電性層の双方ともを前記はんだマスク層領域から、前記少なくとも1つのコンタクト領域上にはんだ堆積物層を残して除去するのに十分な量をエッチ除去することを含んでなる、はんだ堆積物を基板上に形成する方法。 - 工程i)と工程ii)との間に次の工程:
a)前記基板の少なくとも1つの銅表面108上に配置されるフォトレジスト層を形成し、かつ前記フォトレジスト層を回路構成のネガ像に構造化し、
b)前記パターン形成されたフォトレジストを通じて露出される少なくとも1つの銅表面108の部分をエッチ除去し、
c)前記フォトレジストを除去することを含んでなる、請求項1記載の方法。 - 少なくとも1つの内層パッドを露出するための少なくとも1つの開口部が形成される、請求項1又は2記載の方法。
- 少なくとも1つの開口部が工程ii)後に形成される、請求項3記載の方法。
- 少なくとも1つの開口部が工程ii)前に形成される、請求項3記載の方法。
- 次の工程:
i)少なくとも1つのコンタクト領域を含む電気回路構成を有する表面を含む基板を準備し、
ii)前記基板表面上に配置され、かつパターン形成されるはんだマスク層を形成して前記少なくとも1つのコンタクト領域を露出させ、
iii)前記はんだマスク層及び前記少なくとも1つのコンタクト領域を含む基板領域全体を、導電性層を前記基板表面上に設けるのに適した溶液と接触させ、
iv)スズ又はスズ合金を含有するはんだ堆積物層を前記導電性層上へ電気めっきし、
iva)前記はんだ堆積物層上のエッチレジストを、前記少なくとも1つのコンタクト領域の上にある少なくとも前記表面領域上に設け、
v)スズ又はスズ合金を含有する前記はんだ堆積物層及び前記導電性層を、前記はんだ堆積物層と前記導電性層の双方ともを前記はんだマスク層領域から、前記少なくとも1つのコンタクト領域上にはんだ堆積物層を残して除去するのに十分な量をエッチ除去し、
vi)前記エッチレジストを除去することを含んでなる、請求項1から5までのいずれか1項記載の方法。 - 次の工程:
i)少なくとも1つのコンタクト領域を含む電気回路構成を有する表面を含む基板を準備し、
ii)前記基板表面上に配置され、かつパターン形成されるはんだマスク層を形成して前記少なくとも1つのコンタクト領域を露出させ、
iia)付加的なレジスト層を前記はんだマスク層上に形成し、
iii)前記レジスト及びはんだマスク層及び前記少なくとも1つのコンタクト領域を含む基板領域全体を、導電性層を前記基板表面上に設けるのに適した溶液と接触させ、
iv)スズ又はスズ合金を含有するはんだ堆積物層を前記導電性層上へ電気めっきし、
v)スズ又はスズ合金を含有する前記はんだ堆積物層及び前記導電性層を、前記はんだ堆積物層と前記導電性層の双方ともを前記レジスト層領域から、前記少なくとも1つのコンタクト領域上のはんだ材料層を残して除去するのに十分な量をエッチ除去し、
v)前記レジスト層を除去することを含んでなる、請求項1記載の方法。 - 前記スズ又はスズ合金が、
・スズイオンの少なくとも1つの源
・少なくとも1つの酸
・芳香族アルデヒド、芳香族ケトン及びα−/β−不飽和カルボン酸からなる群から選択される少なくとも1つのレベリング剤及び
・少なくとも1つの酸化防止剤
を含んでなる組成物から堆積される、請求項1から7までのいずれか1項記載の方法。 - 少なくとも1つの芳香族のアルデヒド又はケトンが、ベンジリデンアセトン、ベンズアルデヒド、3−クロロベンズアルデヒド、4−クロロベンズアルデヒド、2,4−ジクロロベンズアルデヒド、2,6−ジクロロベンズアルデヒド、2,4,6−トリクロロベンズアルデヒド、1−ナフトアルデヒド、2−ナフトアルデヒド、2−ヒドロキシベンズアルデヒド、3−ヒドロキシベンズアルデヒド、4−ヒドロキシベンズアルデヒド、2−メチルベンズアルデヒド、3−メチルベンズアルデヒド、4−メチルベンズアルデヒド、m−アニスアルデヒド、o−アニスアルデヒド、p−アニスアルデヒド、2−クロロアセトフェノン、3−クロロアセトフェノン、4−クロロアセトフェノン、2,4−ジクロロアセトフェノン、2,4,6−トリクロロアセトフェノンからなる群から選択される、請求項4記載の方法。
- 少なくとも1つのα−/β−不飽和カルボン酸が、アクリル酸、メタクリル酸、クロトン酸、3−クロロアクリル酸、3,3−ジメチルアクリル酸、2,3−ジメチルアクリル酸、アクリル酸メチル、アクリル酸エチル、n−ブチルアクリラート、イソブチルアクリラート、2−エチルヘキシルアクリラート、エチルメタクリラート、n−ブチルメタクリラート、イソブチルメタクリラート、2−ヒドロキシエチルメタクリラート、2−ヒドロキシプロピルメタクリラート、2−ジメチルアミノエチルメタクリラート、メタクリル酸無水物及びメチルメタクリル酸からなる群から選択される、請求項4記載の方法。
- 少なくとも1つの芳香族アルデヒド又は芳香族ケトン及び少なくとも1つのα−/β−不飽和のカルボン酸の混合物が、レベリング剤として使用される、請求項4から6までのいずれか1項記載の方法。
- バリヤー層が、前記少なくとも1つのコンタクト領域上にめっきされる、請求項1から11までのいずれか1項記載の方法。
- 前記バリヤー層が、銅、スズ、ニッケル、クロム、チタン、金、銅−クロム合金、スズ−鉛合金及びそのいずれの合金からなる群から選択される金属からなる、請求項1から12までのいずれか1項記載の方法。
- 金属の付加的な層が前記はんだ堆積物層上へ堆積される、請求項1から13までのいずれか1項記載の方法。
- 金属の付加的な層が、鉛、銀、銅、ビスマス、アンチモン、亜鉛、ニッケル、アルミニウム、マグネシウム、インジウム、テルル、金及びガリウムからなる群から選択される、請求項14記載の方法。
- 前記コンタクト領域が、バイア又はトレンチを含んでなる、請求項1から15までのいずれか1項記載の方法。
- 前記基板が、リフロープロセスにかけられて、スズ又はスズ合金を含有する前記はんだ堆積物層をリフローさせる、請求項1から16までのいずれか1項記載の方法。
- 前記導電性シード層が、銅の無電解堆積により形成される、請求項1から17までのいずれか1項記載の方法。
- 前記はんだ堆積物層が、スズと、鉛、銀、銅、ビスマス、アンチモン、亜鉛、ニッケル、アルミニウム、マグネシウム、インジウム、テルル、ニッケル及びガリウムからなる群から選択される元素との混合物により製造されるスズ合金である、請求項1から18までのいずれか1項記載の方法。
- 前記基板が、プリント回路板、IC基板又はインターポーザーである、請求項1から19までのいずれか1項記載の方法。
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EP08167159A EP2180770A1 (en) | 2008-10-21 | 2008-10-21 | Method to form solder deposits on substrates |
EP09158715.4 | 2009-04-24 | ||
EP09158725 | 2009-04-24 | ||
EP09158715A EP2244285A1 (en) | 2009-04-24 | 2009-04-24 | Method to form solder deposits on substrates |
EP09158725.3 | 2009-04-24 | ||
PCT/EP2009/063049 WO2010046235A1 (en) | 2008-10-21 | 2009-10-07 | Method to form solder deposits on substrates |
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EP (1) | EP2377376B1 (ja) |
JP (1) | JP2012506628A (ja) |
KR (1) | KR20110070987A (ja) |
CN (1) | CN102187749A (ja) |
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WO (1) | WO2010046235A1 (ja) |
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EP2377376B1 (en) | 2019-08-07 |
US20110189848A1 (en) | 2011-08-04 |
WO2010046235A1 (en) | 2010-04-29 |
CN102187749A (zh) | 2011-09-14 |
US8507376B2 (en) | 2013-08-13 |
TWI437135B (zh) | 2014-05-11 |
EP2377376A1 (en) | 2011-10-19 |
MY158939A (en) | 2016-11-30 |
KR20110070987A (ko) | 2011-06-27 |
TW201026910A (en) | 2010-07-16 |
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