TWI521622B - 金屬凸塊之形成方法 - Google Patents

金屬凸塊之形成方法 Download PDF

Info

Publication number
TWI521622B
TWI521622B TW103116316A TW103116316A TWI521622B TW I521622 B TWI521622 B TW I521622B TW 103116316 A TW103116316 A TW 103116316A TW 103116316 A TW103116316 A TW 103116316A TW I521622 B TWI521622 B TW I521622B
Authority
TW
Taiwan
Prior art keywords
metal
metal bump
forming
bump
slot
Prior art date
Application number
TW103116316A
Other languages
English (en)
Other versions
TW201543589A (zh
Inventor
何青原
李昌駿
Original Assignee
中原大學
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中原大學 filed Critical 中原大學
Priority to TW103116316A priority Critical patent/TWI521622B/zh
Priority to US14/461,703 priority patent/US9129957B1/en
Publication of TW201543589A publication Critical patent/TW201543589A/zh
Application granted granted Critical
Publication of TWI521622B publication Critical patent/TWI521622B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13011—Shape comprising apertures or cavities, e.g. hollow bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

金屬凸塊之形成方法
本發明係關於一種金屬凸塊之形成方法，尤指一種利用微影製程形成具有金屬凸塊成形預留槽與金屬凸塊槽縫預留部之光阻層，進而形成具有金屬凸塊槽縫之金屬凸塊之形成方法。
一般來說，現有的電子產品大都需要仰賴IC(積體電路)晶片來進行運作，如記憶體或面板驅動晶片等，而隨著技術的發展，IC晶片之尺寸有著越來越小的趨勢，然而，若是只有IC晶片的製程技術有所改良，而後段的封裝技術卻沒跟上的話，即使IC晶片的尺寸縮得再小也無法將其特性有效的發揮出來。
在IC晶片的封裝技術中，其中之一者是以金屬凸塊製程與IC晶片最後段之金屬墊片(pad)接合，而為了提高接合密度，通常是使用微影技術來形成金屬墊片。然而，當金屬凸塊在化學電鍍後，為了提升特性與調整硬度，往往需要加做回火步驟，使金屬墊片的特性與硬度可再改善。其中，由於金屬凸塊與金屬墊片之間夾有保護層，而保護層與金屬墊片以及金屬凸塊的熱膨脹係數存在有 差異，因此在回火的過程中，保護層與金屬凸塊之間很容易有龜裂的現象發生。
請參閱第一圖，第一圖係顯示先前技術之封裝晶片之平面示意圖。如圖所示，一封裝晶片PA100包含一IC晶片PA1以及一金屬凸塊PA2。IC晶片PA1具有一金屬墊片PA11以及一保護層PA12，金屬墊片PA11係自保護層PA12露出。其中，當封裝晶片PA100進行回火步驟時，通常會在保護層PA12與金屬墊片PA11以及金屬凸塊PA2的接合處CR1發生龜裂現象。
請參閱第二圖，第二圖係顯示先前技術之另一封裝晶片之平面示意圖。如圖所示，一封裝晶片PA100a包含一IC晶片PA1a以及一金屬凸塊PA2a。IC晶片PA1a具有一金屬墊片PA11a、一保護層PA12a以及複數個金屬線PA13a，金屬墊片PA11a係自保護層PA12a露出，而金屬線係鄰近於金屬墊片PA11，且被保護層PA12a所包覆著。其中，由於多個金屬線彼此之間的間距極小，因此在形成保護層PA12a時，往往會因為金屬線之間的空氣跑不出來而形成氣室PA121a，當封裝晶片PA100a進行回火步驟時，除了在保護層PA12a與金屬墊片PA11a以及金屬凸塊PA2a的接合處容易發生龜裂現象外，保護層PA12a與金屬線之接合處CR2也容易因為位於金屬線之間的氣室PA121a而發生龜裂現象。
有鑒於在習知技術中，在需要透過回火處理來調整形成 在IC晶片上之金屬凸塊的特性與硬度時，由於金屬凸塊與保護層的熱膨脹係數存在有一定的差異，因此保護層往往容易在回火的過程中龜裂。
緣此，本發明之主要目的係提供一種金屬凸塊之形成方法，藉以在利用微影製程形成具有金屬凸塊成形預留槽之光阻層時，更同時在金屬凸塊成形預留槽內形成金屬凸塊槽縫預留部，使得金屬凸塊形成時會受到金屬凸塊槽縫預留部的阻擋而在光阻層清除後形成金屬凸塊槽縫。
承上所述，本發明為解決習知技術之問題所採用之必要技術手段係提供一種金屬凸塊之形成方法，係將一金屬凸塊形成於一積體電路晶片上，積體電路晶片具有一保護層與一金屬墊片，金屬墊片係自保護層曝露出，金屬凸塊之形成方法包括以下步驟：首先，是以一微影製程於積體電路晶片上形成一光阻層，光阻層包括一金屬凸塊成形預留槽與一金屬凸塊槽縫預留部，金屬凸塊成形預留槽之範圍係涵蓋金屬墊片，金屬凸塊槽縫預留部係於金屬凸塊成形預留槽內形成於金屬墊片上；接著，以一沉積製程於金屬凸塊成形預留槽內沉積形成金屬凸塊，並使金屬凸塊槽縫預留部穿設於金屬凸塊中；然後，將光阻層清除，使金屬凸塊槽縫預留部清除後形成一開設於金屬凸塊之金屬凸塊槽縫。
如上所述，藉由微影製程形成具有金屬凸塊槽縫預留部之光阻層，使金屬凸塊在形成時會受到金屬凸塊槽縫預留部的影響而不會形成整塊的金屬凸塊，然後在光阻層 清除後便會使金屬凸塊具有一金屬凸塊槽縫；因此，當金屬凸塊回火時，即可藉由此金屬凸塊槽縫來吸收金屬凸塊回火時的熱應力，有效的避免金屬凸塊與保護層因熱膨脹係數存在差異而容易產生龜裂的情形。
由上述之必要技術手段所衍生之一附屬技術手段為，積體電路晶片更具有複數個金屬線，金屬線係鄰近於金屬墊片，保護層係包覆地設置於金屬線上，而在形成光阻層之步驟中，金屬凸塊成形預留槽之範圍更涵蓋金屬線，且光阻層更包括一金屬線槽縫預留部，金屬線槽縫預留部係形成於保護層上，並位於金屬線之範圍內。較佳者，在形成金屬凸塊之步驟中，金屬線槽縫預留部係穿設於金屬凸塊中；此外，在清除光阻層之步驟中，更使金屬線槽縫預留部清除後形成一開設於金屬凸塊之金屬線槽縫。其中，藉由金屬線槽縫預留部的結構，可使金屬凸塊形成金屬線槽縫，而金屬線槽縫則可有效的吸收金屬凸塊回火時的熱應力，避免保護層在金屬線處龜裂。
由上述之必要技術手段所衍生之一附屬技術手段為，沉積製程係為一電鍍製程。
由上述之必要技術手段所衍生之一附屬技術手段為，於清除光阻層之步驟後更包含一步驟，其係對金屬凸塊進行一回火處理，藉以改善金屬凸塊的硬度與特性。
由上述之必要技術手段所衍生之一附屬技術手段為，保護層係為一半導體化合物。
由上述之必要技術手段所衍生之一附屬技術手段為，金 屬墊片係為一鋁墊片。
本發明所採用的具體實施例，將藉由以下之實施例及圖式作進一步之說明。
PA100、PA100a‧‧‧封裝晶片
PA1、PA1a‧‧‧IC晶片
PA2、PA2a‧‧‧金屬凸塊
PA11、PA11a‧‧‧金屬墊片
PA12、PA12a‧‧‧保護層
PA121a‧‧‧氣室
CR1、CR2‧‧‧接合處
100‧‧‧封裝晶片
1‧‧‧積體電路晶片
11‧‧‧保護層
12‧‧‧金屬墊片
13‧‧‧金屬線
2‧‧‧光阻層
21‧‧‧金屬凸塊成形預留槽
22‧‧‧金屬凸塊槽縫預留部
23‧‧‧金屬線槽縫預留部
3‧‧‧金屬凸塊
31‧‧‧金屬凸塊槽縫
32‧‧‧金屬線槽縫
第一圖係顯示先前技術之封裝晶片之平面示意圖；第二圖係顯示先前技術之另一封裝晶片之平面示意圖；第三圖係顯示本發明於積體電路晶片上形成一光阻層之平面示意圖；第四圖係顯示本發明於光阻層之金屬凸塊成形預留槽沉積金屬凸塊之平面示意圖；以及第五圖係顯示第四圖之光阻層清除後之平面示意圖。
請一併參閱第三圖至第五圖，第三圖係顯示本發明於積體電路晶片上形成一光阻層之平面示意圖；第四圖係顯示本發明於光阻層之金屬凸塊成形預留槽沉積金屬凸塊之平面示意圖；第五圖係顯示第四圖之光阻層清除後之平面示意圖。
如圖所示，一種金屬凸塊之形成方法，係應用於一積體電路晶片1之封裝製程中，積體電路晶片1具有一保護層11、一金屬墊片12以及複數個金屬線13，而金屬墊片12係自保護層11之開槽曝露出，金屬線13係鄰近於金屬墊片12，且保護層11係包覆地設置於金屬線13上。其中，保護層11係為半導體化合物，例如為一氮化矽化 合物，而金屬墊片12係為一鋁墊片。
承上所述，金屬凸塊之形成方法首先是以一微影製程於積體電路晶片1上形成一光阻層2，光阻層2包括一金屬凸塊成形預留槽21、一金屬凸塊槽縫預留部22以及複數個金屬線槽縫預留部23。其中，金屬凸塊成形預留槽21之範圍係涵蓋整個金屬墊片12與所有的金屬線13。金屬凸塊槽縫預留部22係於金屬凸塊成形預留槽21內形成於金屬墊片12上。金屬線槽縫預留部23係於金屬凸塊成形預留槽21內形成於保護層11上，並位於金屬線13所在之範圍內。在實際運用上，微影製程係為一黃光微影製程。
接著是以一沉積製程於金屬凸塊成形預留槽21內沉積形成一金屬凸塊3，並使金屬凸塊槽縫預留部22以及金屬線槽縫預留部23穿設於金屬凸塊3中。在實務運用上，沉積製程係為一電鍍製程，而金屬凸塊3例如為銅等導電金屬。
然後是將光阻層2清除以形成一封裝晶片100，使金屬凸塊槽縫預留部22清除後形成一開設於金屬凸塊3之金屬凸塊槽縫31，並使金屬線槽縫預留部23於清除後形成複數個開設於金屬凸塊3之金屬線槽縫32。
最後，對金屬凸塊3進行一回火處理，使金屬凸塊3之原子可重新排列而改善金屬凸塊3之特性與密度。
綜上所述，由於本發明是利用微影製程形成具有金屬凸塊成形預留槽、金屬凸塊槽縫預留部以及金屬線槽縫預留部之光阻層，因此在利用沉積製程沉積形成金屬凸塊 時，金屬凸塊只會形成在金屬凸塊成形預留槽中，且因為金屬凸塊槽縫預留部與金屬線槽縫預留部是位於金屬凸塊成形預留槽內，因此金屬凸塊形成時會使金屬凸塊槽縫預留部與金屬線槽縫預留部位於金屬凸塊內，然後將光阻層清除時，金屬凸塊自然會因為金屬凸塊槽縫預留部與金屬線槽縫預留部被清除掉而產生金屬凸塊槽縫與金屬線槽縫。
其中，藉由金屬凸塊槽縫與金屬線槽縫的形成，當金屬凸塊進行回火處理時，即可透過金屬凸塊槽縫與金屬線槽縫來降低金屬凸塊受熱時所產生的應力，並且有效的防止熱應力造成保護層產生龜裂現象。
此外，相較於先前技術而言，本發明在不需要額外增加製程步驟的情況下，意即只需以一道光罩即可有效的透過光阻層圖案設計的不同而使得最後形成的金屬凸塊具有槽縫，進而使金屬凸塊不會因為與保護層的熱膨脹係數不同而產生龜裂。
藉由以上較佳具體實施例之詳述，係希望能更加清楚描述本發明之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。
100‧‧‧封裝晶片
1‧‧‧積體電路晶片
11‧‧‧保護層
12‧‧‧金屬墊片
13‧‧‧金屬線
3‧‧‧金屬凸塊
31‧‧‧金屬凸塊槽縫
32‧‧‧金屬線槽縫

Claims (8)

  1. 一種金屬凸塊之形成方法，係將一金屬凸塊形成於一積體電路晶片上，該積體電路晶片具有一保護層與一金屬墊片，該金屬墊片係自該保護層曝露出，該金屬凸塊之形成方法包括以下步驟：(a)以一微影製程於該積體電路晶片上形成一光阻層，該光阻層包括一金屬凸塊成形預留槽與一金屬凸塊槽縫預留部，該金屬凸塊成形預留槽之範圍係涵蓋該金屬墊片，該金屬凸塊槽縫預留部係於該金屬凸塊成形預留槽內形成於該金屬墊片上；(b)以一沉積製程於該金屬凸塊成形預留槽內沉積形成該金屬凸塊，並使該金屬凸塊槽縫預留部穿設於該金屬凸塊中；以及(c)將該光阻層清除，使該金屬凸塊槽縫預留部清除後形成一開設於該金屬凸塊之金屬凸塊槽縫。
  2. 如申請專利範圍第1項所述之金屬凸塊之形成方法，其中，該積體電路晶片更具有複數個金屬線，該些金屬線係鄰近於該金屬墊片，該保護層係包覆地設置於該些金屬線上，而在步驟(a)中，該金屬凸塊成形預留槽之範圍更涵蓋該些金屬線，且該光阻層更包括一金屬線槽縫預留部，該金屬線槽縫預留部係形成於該保護層上，並位於該些金屬線之範圍內。
  3. 如申請專利範圍第2項所述之金屬凸塊之形成方法，其中， 在步驟(b)中，該些金屬線槽縫預留部係穿設於該金屬凸塊中。
  4. 如申請專利範圍第3項所述之金屬凸塊之形成方法，其中，在步驟(c)中更使該金屬線槽縫預留部清除後形成一開設於該金屬凸塊之金屬線槽縫。
  5. 如申請專利範圍第1項所述之金屬凸塊之形成方法，其中，該沉積製程係為一電鍍製程。
  6. 如申請專利範圍第1項所述之金屬凸塊之形成方法，其中，於步驟(c)之後更包含一步驟(d)，步驟(d)係對該金屬凸塊進行一回火處理。
  7. 如申請專利範圍第1項所述之金屬凸塊之形成方法，其中，該保護層係為一半導體化合物。
  8. 如申請專利範圍第1項所述之金屬凸塊之形成方法，其中，該金屬墊片係為一鋁墊片。
TW103116316A 2014-05-07 2014-05-07 金屬凸塊之形成方法 TWI521622B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW103116316A TWI521622B (zh) 2014-05-07 2014-05-07 金屬凸塊之形成方法
US14/461,703 US9129957B1 (en) 2014-05-07 2014-08-18 Method of forming a metal bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103116316A TWI521622B (zh) 2014-05-07 2014-05-07 金屬凸塊之形成方法

Publications (2)

Publication Number Publication Date
TW201543589A TW201543589A (zh) 2015-11-16
TWI521622B true TWI521622B (zh) 2016-02-11

Family

ID=54012650

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103116316A TWI521622B (zh) 2014-05-07 2014-05-07 金屬凸塊之形成方法

Country Status (2)

Country Link
US (1) US9129957B1 (zh)
TW (1) TWI521622B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6168915B2 (ja) * 2013-08-22 2017-07-26 キヤノン株式会社 半導体装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI253888B (en) * 2004-12-09 2006-04-21 Advanced Semiconductor Eng Method of packaging flip chip and method of forming pre-solders on substrate thereof
CN102187749A (zh) * 2008-10-21 2011-09-14 埃托特克德国有限公司 用于在衬底上形成焊料沉积物的方法
EP2405469B1 (en) * 2010-07-05 2016-09-21 ATOTECH Deutschland GmbH Method to form solder alloy deposits on substrates
EP2405468A1 (en) * 2010-07-05 2012-01-11 ATOTECH Deutschland GmbH Method to form solder deposits on substrates

Also Published As

Publication number Publication date
TW201543589A (zh) 2015-11-16
US9129957B1 (en) 2015-09-08

Similar Documents

Publication Publication Date Title
TWI523189B (zh) 層疊封裝裝置的形成方法
TW201640629A (zh) 半導體裝置
KR102250997B1 (ko) 반도체 패키지
KR20160052330A (ko) 반도체 장치 및 반도체 장치의 제조 방법
CN102969305A (zh) 用于半导体结构的管芯对管芯间隙控制及其方法
TW201530693A (zh) 用於製造貫通基板穿孔及前側結構之器件、系統及方法
US9349678B2 (en) Chip having a pillar electrode offset from the bonding pad
TW201432857A (zh) 倒裝晶片封裝結構及其製作方法
US20170005024A1 (en) Semiconductor device
CN106449449B (zh) 一种晶圆键合结构的制造方法
TWI637478B (zh) 晶圓及其形成方法
TWI521622B (zh) 金屬凸塊之形成方法
CN104517921B (zh) 键合基底及其形成方法、三维封装结构及其形成方法
KR100853193B1 (ko) 반도체 소자 및 그 형성방법
JP6277174B2 (ja) 窒化アルミニウムと銅コーティング層とのインターフェースにおける応力を改善できるコーティング構造
JP5849602B2 (ja) 発光装置
CN108630595A (zh) 硅通孔的形成方法
US11469151B2 (en) Relating to passivation layers
US9214511B2 (en) Integrated inductor and integrated inductor fabricating method
CN106449580B (zh) 一种晶圆键合结构
JPWO2010119570A1 (ja) 積層半導体装置及び積層半導体装置の製造方法
KR100694420B1 (ko) 반도체소자의 형성방법
KR100650264B1 (ko) 반도체소자의 금속절연막 형성방법
JP6149476B2 (ja) 半導体装置の製造方法
US20240170367A1 (en) Semiconductor device

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees