JP2012238372A - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP2012238372A JP2012238372A JP2012099368A JP2012099368A JP2012238372A JP 2012238372 A JP2012238372 A JP 2012238372A JP 2012099368 A JP2012099368 A JP 2012099368A JP 2012099368 A JP2012099368 A JP 2012099368A JP 2012238372 A JP2012238372 A JP 2012238372A
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- oxide semiconductor
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- 229910052758 niobium Inorganic materials 0.000 description 1
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- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- GVGCUCJTUSOZKP-UHFFFAOYSA-N nitrogen trifluoride Chemical compound FN(F)F GVGCUCJTUSOZKP-UHFFFAOYSA-N 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 238000007500 overflow downdraw method Methods 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229910052700 potassium Inorganic materials 0.000 description 1
- 239000011591 potassium Substances 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
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- 230000004044 response Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000007725 thermal activation Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/263—Amorphous materials
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
- G11C15/046—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using non-volatile storage elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
Abstract
【解決手段】酸化物半導体を半導体層に有する第1のトランジスタ及び当該第1のトランジスタをオフ状態とすることで書き込んだデータに対応する電位を保持できる容量素子を有するメモリ回路と、書き込んだ電位を参照するための参照回路を有し、参照回路を構成する第2のトランジスタの導通状態を検出することで、整合するデータのアドレスを取得し、高速な検索機能を可能にした半導体記憶装置である。
【選択図】図1
Description
本実施の形態では、CAMとして動作可能な半導体記憶装置の構成について、図1を用いて説明する。
本実施の形態では、上記実施の形態1で説明した、CAMとして動作可能な半導体記憶装置の具体的な構成を示し、その構成及び動作の一例について図2乃至図5を用いて説明する。
本実施の形態では、実施の形態1で示した参照回路における第2のトランジスタの構成について複数の形態を例示する。
本実施の形態では、本発明の一態様に係る半導体記憶装置であるCAMを適用可能なCPUの構成について説明する。
図6(A)に示した、チャネルがシリコンに形成される場合における第2のトランジスタ133Aと、チャネルが酸化物半導体層に形成される第1のトランジスタ131と、容量素子132とを例に挙げて、半導体記憶装置の作製方法について説明する。
101 メモリセル
102 判定回路
103 電源線
131 トランジスタ
132 容量素子
700 基板
701 絶縁膜
702 半導体膜
703 ゲート絶縁膜
704 半導体層
707 ゲート電極
709 不純物領域
710 チャネル形成領域
712 絶縁膜
713 絶縁膜
716 酸化物半導体層
719 導電膜
720 導電膜
721 ゲート絶縁膜
722 ゲート電極
723 導電膜
724 絶縁膜
725 開口部
726 配線
727 絶縁膜
101A メモリセル
101B メモリセル
111A メモリ回路
111B メモリ回路
112A 参照回路
112B 参照回路
121A トランジスタ
121B トランジスタ
122A 容量素子
122B 容量素子
123A トランジスタ
123B トランジスタ
133A トランジスタ
133B トランジスタ
9900 基板
9901 ALU
9902 ALU・Controller
9903 Instruction・Decoder
9904 Interrupt・Controller
9905 Timing・Controller
9906A CAM
9906B Register
9907 Memory・Controller
9908 Bus・I/F
9909 ROM
9920 ROM・I/F
Claims (6)
- 第1端子がビット線に電気的に接続され、ゲートがワード線に電気的に接続され、酸化物半導体を半導体層に有する第1のトランジスタと、第1電極が前記第1のトランジスタの第2端子に電気的に接続され、第2電極がデータ線に電気的に接続された容量素子とを、有するメモリ回路と、
ゲートが前記第1のトランジスタの第2端子及び前記容量素子の第1電極に電気的に接続された第2のトランジスタを有する参照回路と、を有する複数のメモリセルを有し、
前記複数のメモリセルが、前記ビット線が延設された方向及び前記ワード線が延設された方向に複数設けられ、
前記ワード線が延設された方向に隣接する前記メモリセル間では、前記第2のトランジスタの第1端子と第2端子とが電気的に直列接続されており、当該直列接続された前記第2のトランジスタには判定回路が電気的に接続される半導体記憶装置。 - 請求項1において、前記第2のトランジスタが単結晶シリコンを半導体層に有する半導体記憶装置。
- 請求項2において、前記第1のトランジスタと前記第2のトランジスタとが積層して設けられている半導体記憶装置。
- 請求項1において、前記第2のトランジスタが酸化物半導体を半導体層に有する半導体記憶装置。
- 請求項4において、前記第1のトランジスタの半導体層と前記第2のトランジスタの半導体層とが同じ層に設けられる半導体記憶装置。
- 請求項1乃至請求項5のいずれか一において、前記判定回路は前記直列接続された前記第2のトランジスタの導通状態または非導通状態に応じた電位の変動を検出する回路である半導体記憶装置。
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