JP2012174870A - 多層配線基板 - Google Patents
多層配線基板 Download PDFInfo
- Publication number
- JP2012174870A JP2012174870A JP2011035004A JP2011035004A JP2012174870A JP 2012174870 A JP2012174870 A JP 2012174870A JP 2011035004 A JP2011035004 A JP 2011035004A JP 2011035004 A JP2011035004 A JP 2011035004A JP 2012174870 A JP2012174870 A JP 2012174870A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductive pad
- wiring board
- multilayer wiring
- barrier metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01084—Polonium [Po]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
【解決手段】導体層及び樹脂絶縁層が交互に積層されてなるビルドアップ層と、前記樹脂絶縁層の表面から突出して形成され、下部に位置する円柱部及び上部に位置する凸部からなる導電性パッドと、を備え、前記導電性パッドの前記凸部の表面は、連続した曲面形状であるようにして多層配線基板を構成する。
【選択図】図4
Description
導体層及び樹脂絶縁層が交互に積層されてなるビルドアップ層と、
前記樹脂絶縁層の表面から突出して形成され、下部に位置する円柱部及び上部に位置する凸部からなる導電性パッドと、
を備え、
前記導電性パッドの前記凸部の表面は、連続した曲面形状であることを特徴とする、多層配線基板に関する。
図1及び図2は、本実施形態における多層配線基板の平面図であり、図1は、多層配線基板を上側から見た場合の状態を示し、図2は、多層配線基板を下側から見た場合の状態を示している。また、図3は、図1及び2に示す多層配線基板をI−I線に沿って切った場合の断面の一部を拡大して示す図であり、図4は、図3に示す導電性パッドの近傍を拡大して示す断面図である。
次に、図1〜図4に示す多層配線基板10の製造方法について説明する。図5〜図14は、本実施形態における多層配線基板10の製造方法における工程図である。
11 支持基板
13 プリプレグ
14 剥離シート
15 マスクパターン
21 第1の樹脂絶縁層
22 第2の樹脂絶縁層
31 第1の導体層
32 第2の導体層
41 第1のレジスト層
42 第2のレジスト層
51,52,53 ビア導体
61 第1の導電性パッド
62 第2の導電性パッド
621 第2の導電性パッドの円柱部
622 第2の導電性パッドの凸部
63 バリアメタル層
64 はんだ層
Claims (4)
- 導体層及び樹脂絶縁層が交互に積層されてなるビルドアップ層と、
前記樹脂絶縁層の表面から突出して形成され、下部に位置する円柱部及び上部に位置する凸部からなる導電性パッドと、
を備え、
前記導電性パッドの前記凸部の表面は、連続した曲面形状であることを特徴とする、多層配線基板。 - 前記導電性パッドの全面を覆うはんだ層を備えることを特徴とする、請求項1に記載の多層配線基板。
- 前記導電性パッドと前記はんだ層との間に、前記導電性パッドの全面を被覆して形成されたバリアメタル層を備え、
前記はんだ層は、前記導電性パッドの全面を被覆するバリアメタル層を介して前記導電性パッドを覆い、
前記導電性パッドの前記樹脂絶縁層側に位置する側端面上に形成された前記バリアメタル層の被覆厚みは、該側端面よりも上部に位置する前記導電性パッドの表面上に形成された前記バリアメタル層の被覆厚みよりも大きいことを特徴とする、請求項2に記載の多層配線基板。 - 前記はんだ層は、前記バリアメタル層上にのみ形成され、前記樹脂絶縁層とは接触しないことを特徴とする、請求項3に記載の多層配線基板。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011035004A JP5530955B2 (ja) | 2011-02-21 | 2011-02-21 | 多層配線基板 |
US13/399,547 US9119333B2 (en) | 2011-02-21 | 2012-02-17 | Multilayer wiring board |
TW101105393A TWI486104B (zh) | 2011-02-21 | 2012-02-20 | 多層配線板 |
KR20120017072A KR20120097327A (ko) | 2011-02-21 | 2012-02-20 | 다층 배선기판 |
CN201210041461.4A CN102686024B (zh) | 2011-02-21 | 2012-02-21 | 多层配线基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011035004A JP5530955B2 (ja) | 2011-02-21 | 2011-02-21 | 多層配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012174870A true JP2012174870A (ja) | 2012-09-10 |
JP5530955B2 JP5530955B2 (ja) | 2014-06-25 |
Family
ID=46651823
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011035004A Expired - Fee Related JP5530955B2 (ja) | 2011-02-21 | 2011-02-21 | 多層配線基板 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9119333B2 (ja) |
JP (1) | JP5530955B2 (ja) |
KR (1) | KR20120097327A (ja) |
CN (1) | CN102686024B (ja) |
TW (1) | TWI486104B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6191048B1 (ja) * | 2016-03-30 | 2017-09-06 | 住友大阪セメント株式会社 | Fpc付き光変調器、及びそれを用いた光送信装置 |
TWI595812B (zh) * | 2016-11-30 | 2017-08-11 | 欣興電子股份有限公司 | 線路板結構及其製作方法 |
US10325842B2 (en) * | 2017-09-08 | 2019-06-18 | Advanced Semiconductor Engineering, Inc. | Substrate for packaging a semiconductor device package and a method of manufacturing the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03268385A (ja) * | 1990-03-17 | 1991-11-29 | Fujitsu Ltd | はんだバンプとその製造方法 |
JP2004047510A (ja) * | 2002-07-08 | 2004-02-12 | Fujitsu Ltd | 電極構造体およびその形成方法 |
JP2009064973A (ja) * | 2007-09-06 | 2009-03-26 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
JP2010157718A (ja) * | 2008-12-29 | 2010-07-15 | Ibiden Co Ltd | プリント配線板及びプリント配線板の製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR970707444A (ko) * | 1994-10-28 | 1997-12-01 | 야마모토 히데키 | 프로브 구조(probe structure) |
SG73469A1 (en) * | 1996-11-20 | 2000-06-20 | Ibiden Co Ltd | Solder resist composition and printed circuit boards |
US6330967B1 (en) * | 1997-03-13 | 2001-12-18 | International Business Machines Corporation | Process to produce a high temperature interconnection |
JP3701807B2 (ja) * | 1999-01-20 | 2005-10-05 | ソニーケミカル株式会社 | 基板製造方法、及び基板 |
JP3363832B2 (ja) * | 1999-05-13 | 2003-01-08 | アルプス電気株式会社 | 薄膜構造体およびその製造方法 |
JP4293500B2 (ja) * | 2001-05-07 | 2009-07-08 | 第一電子工業株式会社 | 電子部品の製造方法 |
US6767819B2 (en) * | 2001-09-12 | 2004-07-27 | Dow Corning Corporation | Apparatus with compliant electrical terminals, and methods for forming same |
US6888255B2 (en) * | 2003-05-30 | 2005-05-03 | Texas Instruments Incorporated | Built-up bump pad structure and method for same |
JP4329532B2 (ja) * | 2003-07-15 | 2009-09-09 | 日立電線株式会社 | 平角導体及びその製造方法並びにリード線 |
JP2007214427A (ja) | 2006-02-10 | 2007-08-23 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
US7875804B1 (en) * | 2006-09-27 | 2011-01-25 | Hutchinson Technology Incorporated | Plated ground features for integrated lead suspensions |
JP4881211B2 (ja) | 2007-04-13 | 2012-02-22 | 新光電気工業株式会社 | 配線基板の製造方法及び半導体装置の製造方法及び配線基板 |
JP4981712B2 (ja) | 2008-02-29 | 2012-07-25 | 新光電気工業株式会社 | 配線基板の製造方法及び半導体パッケージの製造方法 |
JP5211801B2 (ja) * | 2008-03-28 | 2013-06-12 | Tdk株式会社 | 電子部品 |
JP5203045B2 (ja) | 2008-05-28 | 2013-06-05 | 日本特殊陶業株式会社 | 多層配線基板の中間製品、多層配線基板の製造方法 |
JP2012169591A (ja) * | 2011-01-24 | 2012-09-06 | Ngk Spark Plug Co Ltd | 多層配線基板 |
-
2011
- 2011-02-21 JP JP2011035004A patent/JP5530955B2/ja not_active Expired - Fee Related
-
2012
- 2012-02-17 US US13/399,547 patent/US9119333B2/en not_active Expired - Fee Related
- 2012-02-20 TW TW101105393A patent/TWI486104B/zh not_active IP Right Cessation
- 2012-02-20 KR KR20120017072A patent/KR20120097327A/ko active IP Right Grant
- 2012-02-21 CN CN201210041461.4A patent/CN102686024B/zh not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03268385A (ja) * | 1990-03-17 | 1991-11-29 | Fujitsu Ltd | はんだバンプとその製造方法 |
JP2004047510A (ja) * | 2002-07-08 | 2004-02-12 | Fujitsu Ltd | 電極構造体およびその形成方法 |
JP2009064973A (ja) * | 2007-09-06 | 2009-03-26 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
JP2010157718A (ja) * | 2008-12-29 | 2010-07-15 | Ibiden Co Ltd | プリント配線板及びプリント配線板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20120097327A (ko) | 2012-09-03 |
JP5530955B2 (ja) | 2014-06-25 |
US9119333B2 (en) | 2015-08-25 |
CN102686024A (zh) | 2012-09-19 |
TWI486104B (zh) | 2015-05-21 |
CN102686024B (zh) | 2015-10-07 |
US20120211271A1 (en) | 2012-08-23 |
TW201244561A (en) | 2012-11-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101475109B1 (ko) | 다층배선기판 및 그의 제조방법 | |
JP2012169591A (ja) | 多層配線基板 | |
KR101580343B1 (ko) | 다층 배선기판의 제조방법 | |
TWI507096B (zh) | 多層電路板及其製作方法 | |
KR101215246B1 (ko) | 다층 배선기판의 제조방법 및 다층 배선기판 | |
KR101281410B1 (ko) | 다층 배선기판 | |
JP2009239224A (ja) | 多層配線基板 | |
JP2013149941A (ja) | 多層配線基板及びその製造方法 | |
JP2013187255A (ja) | 配線基板の製造方法 | |
KR101470706B1 (ko) | 다층 배선기판의 제조방법 | |
JP5302920B2 (ja) | 多層配線基板の製造方法 | |
JP2013123035A (ja) | 多層配線基板の製造方法 | |
JP5530955B2 (ja) | 多層配線基板 | |
JP4445777B2 (ja) | 配線基板、及び配線基板の製造方法 | |
JP5302927B2 (ja) | 多層配線基板の製造方法 | |
JP2012156325A (ja) | 多層配線基板の製造方法、及びペースト印刷用マスク | |
JP4549694B2 (ja) | 配線基板の製造方法及び多数個取り基板 | |
JP2012209322A (ja) | 配線基板の製造方法 | |
TWI507109B (zh) | A supporting substrate for manufacturing a multilayer wiring board, and a method for manufacturing the multilayer wiring board | |
JP2015144152A (ja) | 配線基板の製造方法 | |
KR101262584B1 (ko) | 인쇄회로기판 및 그의 제조 방법 | |
JP2012114110A (ja) | 多層配線基板の製造方法 | |
JP2005079107A (ja) | 配線基板の製造方法、及び配線基板 | |
JP2005243980A (ja) | 配線基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130530 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140116 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140121 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140310 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140401 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140421 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5530955 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |