JP2011511436A - 電子基板中の信頼性ある積層ビアのための組込み抑制ディスク - Google Patents
電子基板中の信頼性ある積層ビアのための組込み抑制ディスク Download PDFInfo
- Publication number
- JP2011511436A JP2011511436A JP2010543474A JP2010543474A JP2011511436A JP 2011511436 A JP2011511436 A JP 2011511436A JP 2010543474 A JP2010543474 A JP 2010543474A JP 2010543474 A JP2010543474 A JP 2010543474A JP 2011511436 A JP2011511436 A JP 2011511436A
- Authority
- JP
- Japan
- Prior art keywords
- disk
- constraining
- restraining
- substrate
- suppression
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structure Of Printed Boards (AREA)
Abstract
【解決手段】積層ビアのための基板ビア構造体は、各ビアがランド内に配置された積層された複数のビアと、該基板ビア構造の面内の変形を抑制するための、少なくとも一つののビアを取り巻く少なくとも一つの抑制ディスクとを含む。抑制ディスクは、該抑制ディスクが2つの樹脂層の間に配置されるように組込まれる。この抑制ディスクは銅で作製することができる。該抑制ディスクは円形もしくは方形とするができる。望ましくは、抑制ディスクとビアとの間には絶縁ギャップが設けられる。
【選択図】図3
Description
Claims (16)
- 基板を含む基板ビア構造体であって、
前記基板は、
各ビアがランド内に配置された複数の積層されたビアと、
前記複数の積層されたビアの少なくとも一つを取り巻く少なくとも一つの抑制ディスクであって、前記少なくとも一つの抑制ディスクは前記基板ビア構造体の面内変形を抑制する、前記抑制ディスクと、
を包含する、前記構造体。 - 前記抑制ディスクは、前記抑制ディスクが2つの樹脂層の間に配置されるように組み込まれる、請求項1に記載の構造体。
- 前記抑制ディスクは銅である、請求項2に記載の構造体。
- 前記抑制ディスクはほぼ円環状である、請求項3に記載の構造体。
- 前記抑制ディスクは方形状である、請求項3に記載の構造体。
- 前記抑制ディスクと前記ビアとの間に絶縁ギャップをさらに含む、請求項1に記載の構造体。
- 前記抑制ディスクの形状は、設計パラメータと接続回路がかける抑制とに応じて変えられる、請求項2に記載の構造体。
- 前記積層されたビアは銅ビアである、請求項1に記載の構造体。
- 前記抑制ディスクはエッチング形成される、請求項1に記載の構造体。
- 前記抑制ディスクは、サブトラクティブ・エッチング工程を用いてエッチングされる、請求項9に記載の構造体。
- ビア積層の面内変形を抑制する方法であって、
前記方法は、
基板中に、各ビアがランド内に配置されたビア積層を生成するステップと、
抑制ディスクを生成するステップと、
前記ビア積層の面内変形を抑制するため、前記抑制ディスクが前記ビアのランドを取り巻くように、前記抑制ディスクを組み込むステップと、
を含む、前記方法。 - 前記組み込むステップは、前記抑制ディスクの内径と前記ビアのランドとの間に絶縁ギャップを生成するステップをさらに含む、請求項11に記載の方法。
- 前記組み込むステップは、2つの樹脂層の間に前記抑制ディスクを配置するステップを含む、請求項11に記載の方法。
- 前記抑制ディスクを生成するステップは、前記抑制ディスクを銅で生成するステップを含む、請求項11に記載の方法。
- 前記抑制ディスクを生成するステップは、円環状ディスクを生成するステップをさらに含む、請求項14に記載の方法。
- 前記抑制ディスクを生成する前記ステップは、前記基板中の利用可能なスペースに適合するように、前記抑制ディスクの形状を調整するステップをさらに含む、請求項14に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/020,561 US20090189289A1 (en) | 2008-01-27 | 2008-01-27 | Embedded constrainer discs for reliable stacked vias in electronic substrates |
US12/020,561 | 2008-01-27 | ||
PCT/EP2009/050585 WO2009124785A1 (en) | 2008-01-27 | 2009-01-20 | Embedded constrainer discs for reliable stacked vias in electronic substrates |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2011511436A true JP2011511436A (ja) | 2011-04-07 |
JP2011511436A5 JP2011511436A5 (ja) | 2012-08-23 |
JP5182827B2 JP5182827B2 (ja) | 2013-04-17 |
Family
ID=40898382
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010543474A Expired - Fee Related JP5182827B2 (ja) | 2008-01-27 | 2009-01-20 | 電子基板中の信頼性ある積層ビアのための組込み抑制ディスク |
Country Status (8)
Country | Link |
---|---|
US (1) | US20090189289A1 (ja) |
EP (1) | EP2238620B1 (ja) |
JP (1) | JP5182827B2 (ja) |
KR (1) | KR101285030B1 (ja) |
CN (1) | CN101926000A (ja) |
AT (1) | ATE521989T1 (ja) |
TW (1) | TW200947657A (ja) |
WO (1) | WO2009124785A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI449152B (zh) * | 2011-12-21 | 2014-08-11 | Ind Tech Res Inst | 半導體元件堆疊結構 |
US11270955B2 (en) * | 2018-11-30 | 2022-03-08 | Texas Instruments Incorporated | Package substrate with CTE matching barrier ring around microvias |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08172264A (ja) * | 1994-12-20 | 1996-07-02 | Hitachi Chem Co Ltd | 多層配線板および金属箔張り積層板の製造法 |
JP2002305379A (ja) * | 2001-02-05 | 2002-10-18 | Tdk Corp | 多層基板及びその製造方法 |
JP2003163453A (ja) * | 2001-11-27 | 2003-06-06 | Matsushita Electric Works Ltd | 多層配線板の製造方法及び多層配線板 |
JP2005251792A (ja) * | 2004-03-01 | 2005-09-15 | Fujitsu Ltd | 配線基板およびその製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4204150B2 (ja) * | 1998-10-16 | 2009-01-07 | パナソニック株式会社 | 多層回路基板 |
TW430935B (en) * | 1999-03-19 | 2001-04-21 | Ind Tech Res Inst | Frame type bonding pad structure having a low parasitic capacitance |
JP2005011883A (ja) | 2003-06-17 | 2005-01-13 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置および配線基板の製造方法 |
JP2005019730A (ja) * | 2003-06-26 | 2005-01-20 | Kyocera Corp | 配線基板およびそれを用いた電子装置 |
KR20050072881A (ko) * | 2004-01-07 | 2005-07-12 | 삼성전자주식회사 | 임피던스 정합 비아 홀을 구비하는 다층기판 |
US7523545B2 (en) * | 2006-04-19 | 2009-04-28 | Dynamic Details, Inc. | Methods of manufacturing printed circuit boards with stacked micro vias |
JP2008124398A (ja) * | 2006-11-15 | 2008-05-29 | Shinko Electric Ind Co Ltd | 半導体パッケージおよびその製造方法 |
-
2008
- 2008-01-27 US US12/020,561 patent/US20090189289A1/en not_active Abandoned
-
2009
- 2009-01-05 TW TW098100116A patent/TW200947657A/zh unknown
- 2009-01-20 EP EP09731078A patent/EP2238620B1/en not_active Not-in-force
- 2009-01-20 JP JP2010543474A patent/JP5182827B2/ja not_active Expired - Fee Related
- 2009-01-20 KR KR1020107016530A patent/KR101285030B1/ko not_active IP Right Cessation
- 2009-01-20 CN CN2009801029748A patent/CN101926000A/zh active Pending
- 2009-01-20 WO PCT/EP2009/050585 patent/WO2009124785A1/en active Application Filing
- 2009-01-20 AT AT09731078T patent/ATE521989T1/de not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08172264A (ja) * | 1994-12-20 | 1996-07-02 | Hitachi Chem Co Ltd | 多層配線板および金属箔張り積層板の製造法 |
JP2002305379A (ja) * | 2001-02-05 | 2002-10-18 | Tdk Corp | 多層基板及びその製造方法 |
JP2003163453A (ja) * | 2001-11-27 | 2003-06-06 | Matsushita Electric Works Ltd | 多層配線板の製造方法及び多層配線板 |
JP2005251792A (ja) * | 2004-03-01 | 2005-09-15 | Fujitsu Ltd | 配線基板およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20090189289A1 (en) | 2009-07-30 |
TW200947657A (en) | 2009-11-16 |
EP2238620A1 (en) | 2010-10-13 |
WO2009124785A1 (en) | 2009-10-15 |
EP2238620B1 (en) | 2011-08-24 |
KR20100111280A (ko) | 2010-10-14 |
ATE521989T1 (de) | 2011-09-15 |
KR101285030B1 (ko) | 2013-07-11 |
CN101926000A (zh) | 2010-12-22 |
JP5182827B2 (ja) | 2013-04-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9997466B2 (en) | Integrated circuit stack including a patterned array of electrically conductive pillars | |
US8522430B2 (en) | Clustered stacked vias for reliable electronic substrates | |
US8164165B2 (en) | Wafer-to-wafer stack with supporting pedestal | |
US20190067205A1 (en) | Thermal and electromagnetic interference shielding for die embedded in package substrate | |
TWI462257B (zh) | 空氣矽穿孔結構 | |
JP4844391B2 (ja) | 半導体装置並びに配線基板及びその製造方法 | |
JP2013542596A (ja) | 補強シリコン貫通ビアを備える半導体チップ | |
JP2013537365A (ja) | ポリマー充填剤溝を有する半導体チップデバイス | |
CN104037153A (zh) | 3d封装件及其形成方法 | |
JP2019519930A (ja) | モジュール及び複数のモジュールを製造するための方法 | |
KR20090127278A (ko) | 반도체 장치 및 이 반도체 장치의 제조 방법 | |
TW201342523A (zh) | 用於只包含已驗證的電路板的三維電子模組之集體製造的方法 | |
US9613921B2 (en) | Structure to prevent solder extrusion | |
JP5182827B2 (ja) | 電子基板中の信頼性ある積層ビアのための組込み抑制ディスク | |
WO2016190100A1 (ja) | 配線基板、および製造方法 | |
US20140167276A1 (en) | Substrate for semiconductor package, semiconductor package using the substrate, and method of manufacturing the semiconductor package | |
JP2022525367A (ja) | 集積回路におけるダイ間通信のためのスペーサ | |
CN104576620B (zh) | 半导体封装结构与其制造方法 | |
US7312523B2 (en) | Enhanced via structure for organic module performance | |
US9253880B2 (en) | Printed circuit board including a plurality of circuit layers and method for manufacturing the same | |
JP6361145B2 (ja) | 配線板 | |
Kanbach et al. | 3D Si‐on‐Si stack packaging | |
KR20110021123A (ko) | 전자소자 내장형 인쇄회로기판 | |
Mulla et al. | Reliability of flip chip on flexible substrates under drop impact | |
Lan et al. | Thermo-mechanical reliability of 3D package under different thermal cycling |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20111122 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120626 |
|
A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20120626 |
|
RD12 | Notification of acceptance of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7432 Effective date: 20120626 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20120626 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120810 |
|
A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20120822 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120904 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121107 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20121218 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20121218 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130109 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5182827 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160125 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |