CN101926000A - 用于电子基板内的可靠层叠过孔的嵌入式约束盘 - Google Patents
用于电子基板内的可靠层叠过孔的嵌入式约束盘 Download PDFInfo
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Abstract
一种用于层叠的过孔的基板过孔结构,包括多个层叠的过孔,其中每一个过孔均被设置在平台上;以及至少一个约束盘,其环绕至少一个过孔,用于约束所述基板过孔结构的面内变形。所述约束盘被嵌入以便所述约束盘被设置在两层树脂之间。所述约束盘由铜构成。所述约束盘为圆形或方形。优选地,在所述约束盘与所述过孔之间存在介电间隙。
Description
技术领域
公开的本发明宽泛地涉及电子模块的领域,特别地涉及通过电子模块内层叠的过孔的电连接性的领域。
背景技术
图1示出了电子模块的两个关键部件。芯片由硅构成,且其上方形成有电路。基板由有机材料构成,并嵌入有铜互连。基板有助于将上述芯片接合到主板上的外部电路。
芯片与基板间的连接点(可控制坍塌芯片连接或“C4”)的密度乃是关键参数。大量的C4需要多个构造(buildup)层,以实现所需要的到主板的电连接。图1示出了完成互连所需的层叠以及交错的过孔。相较于交错的过孔而言,层叠的过孔的连接密度高出20%。
图2示出了与层叠的过孔和镀通孔相关的公知技术。由图可知,在构造层内的铜互连围绕层叠的过孔并且其空间分布可以随意变化而不依照特定的设计规则。各种用于构成芯片模块的材料的热膨胀系数(CTE)并不匹配,且被公知在模块内驱动热机械应力。由热机械驱动而累积的应变导致电子模块的重复热循环在过孔界面区域出现故障。由CTE驱动的热机械应力使得过孔叠层沿着Z轴及X-Y平面产生应变。
发明内容
简明地,根据本发明的实施例,一种用于层叠的过孔的基板过孔结构包括:多个层叠的过孔,其中每一个过孔均被设置在平台(landing)上;以及至少一个约束盘,环绕至少一个过孔,用于约束所述基板过孔结构的面内变形。嵌入所述约束盘,以便所述约束盘在两层树脂之间。所述约束盘由铜构成。所述约束盘为圆形或方形。优选地,在所述约束盘与所述过孔之间存在介电间隙。
根据本发明的实施例,一种用于约束过孔叠层的面内变形的方法,所述方法包括:在基板上制造过孔叠层,其中每一个过孔均被设置在平台上;制造约束盘;以及嵌入所述约束盘片,以便使所述约束盘环绕所述过孔平台。
附图说明
为了描述上述和其他示例性的目的、方面和优点,使用本发明的示例性实施例的下列详细描述并结合附图,其中:
图1示出了根据公知技术的基本电子模块;
图2示出了根据公知技术的电子模块的层叠的过孔;
图3a示出了根据本发明的实施例的现有技术的具有周围互连的层叠的过孔;
图3b示出了本发明的实施例的层叠的过孔,其周围有约束盘;
图4示出了本发明的实施例的三维有限元模型的网格结构;
图5示出了层叠的过孔与周围结构的两个工作模型,一个没有约束盘,另一个有约束盘;
图6a示出了本发明的实施例的约束盘的上视图;以及
图6b示出了本发明的实施例的约束盘的侧视剖面图。
虽然寻求保护的本发明可以被修改为备选形式,当在附图中以实例的形式示出了其特定的实施例,并将在这里对其进行详细的描述。然而,应该理解,这里的附图和详细描述不旨在将本发明限定为公开的特定形式而是与此相反,本发明覆盖落入本发明的范围内的所有修改、等价物以及备选。
具体实施方式
在此公开了用于约束面内变形(in-plane deformation)的装置与方法,其中,上述面内变形由环绕过孔叠层的构造层所驱动。现在特别地参考图示,尤其是图3,图中显示了图2的层叠的过孔,以及根据本发明的实施例的约束盘,其中,约束盘片环绕在层叠的过孔周围。在热循环期间(125℃~-55℃),因为构造层(热膨胀系数~30ppm/℃)沿着Z轴以及面内(X-Y)的收缩远快于铜过孔(热膨胀系数~16ppm/℃),所以层叠的过孔受到周围构造层压缩。周围约束盘通过在X-Y方向约束构造层而减少施加于层叠的过孔的负载量。
没有约束盘的话,由高CTE树脂组成的构造层的体积收缩会远多于铜过孔。因此,在冷却或加热有机基板时,有机基板收缩或膨胀都会在铜过孔与树脂之间的界面产生分布力。然而,此分布力是不希望的,因为其在过孔材料上产生塑性应变。此塑性应变依序在层叠的过孔内促进了疲劳开裂的产生及增加。通过在层叠的过孔的周围空间内嵌入约束的(constraining)铜盘,通过分享盘与层叠的过孔之间的表面力,便可以相当地降低树脂在过孔表面上产生的分布力。
参考图4,其示出了三维(3D)有限元模型的网格结构。如图4所示,示出了两个约束盘A与B。图4内的格栅图形代表用于公式化并解决有限元问题的网格结构。此模型的刻度相当于镀通孔平台(landing)直径,亦即210μm。接着,构建两个范例(图5)并进行比较,如图5所示,1)其周围没有环绕约束盘的过孔叠层以及2)具有两个约束盘片的过孔叠层。分析显示,通过双约束盘系统,传统层叠过孔的累积应变可从1.7%降至1.54%(10%降幅)。在此观察到,过孔的寿命非线性依赖于塑性应变。材料内的弹性应变是可逆的,但是塑性应变是不可逆的。当所施加的应力移除时,弹性变形转回其原来的形状,但是塑性应变则不会。当塑性应变因为热循环而重复产生时,会在材料内产生疲劳故障。因此,将关键部件在电子组装时所遭遇的塑性应变最小化是很重要的。
图6a与图6b分别示出圆形约束盘的上视图与侧视图。约束盘的精确形状必须根据位于层叠的过孔附近的互连来决定。理论上,圆形的约束盘是优选的,因为其产生圆形对称限制。但是,基于刚才所提及的理由,形状的改变可能无法避免。例如,当周围空间中的互连密度不高的时候,盘片可以是圆形的且可以增加它们的直径,以分担较多由树脂施加的负载。然而,假如环绕层叠的过孔的空间是较为拥挤的,则需要裁切盘形状,以符合可用的空间。
在三种形式的构造层(接地面、电压面及互连层)中,前两种本身的设计即提供了约束盘片的功能。因此,当存在环绕过孔叠层的铜面时,则不要求约束盘的外显式设计。然而,因为构造层的数目增加,过孔叠层的物需要用于嵌入约束盘的外显式设计。需要一定程度的互连设计变更,以嵌入约束盘。相似于互连,约束盘片夹置于两层树脂之间,在此称为嵌入。
使用用于将层电路化的相同的减成(subtractive)工艺对约束盘进行蚀刻。图6示出了位于约束盘的内径与过孔叠层之间的间隙。必须将位于过孔叠层与盘之间的介电间隙最优化,以在电寄生效应与积极的机械约束效应之间取得平衡。
因此,虽然考虑优选实施例描述了本发明,但本领域的技术人员应理解可以在本发明的精神的范围内进行其他修改。
Claims (16)
1.一种基板过孔结构,包括:
基板,其包括:
多个层叠的过孔,其中每一个过孔均被设置在平台上;以及
至少一个约束盘,环绕所述多个层叠的过孔中的至少一个,所述至少一个约束盘约束所述基板过孔结构的面内变形。
2.根据权利要求1的结构,其中所述约束盘被嵌入以便所述约束盘被设置在两层树脂之间。
3.根据权利要求2的结构,其中所述约束盘为铜。
4.根据权利要求3的结构,其中所述约束盘基本上为圆形。
5.根据权利要求3的结构,其中所述约束盘为方形。
6.根据权利要求1的结构,还包括:在所述约束盘与所述过孔之间的介电间隙。
7.根据权利要求2的结构,其中所述约束盘的形状根据设计参数和互连所施加的限制而变化。
8.根据权利要求1的结构,其中所述层叠的过孔为铜过孔。
9.根据权利要求1的结构,其中蚀刻所述约束盘。
10.根据权利要求1的结构,其中使用减成蚀刻工艺蚀刻所述约束盘。
11.一种用于约束过孔叠层的面内变形的方法,所述方法包括:
在基板上制造过孔叠层,其中每一个过孔均被设置在平台上;
制造约束盘;以及
嵌入所述约束盘,以便所述约束盘环绕所述过孔平台从而约束所述过孔叠层的面内变形。
12.根据权利要求11的方法,其中所述嵌入步骤还包括在所述约束盘的内径与所述过孔平台之间制造介电间隙。
13.根据权利要求11的方法,其中所述嵌入步骤包括将所述约束盘设置在两层树脂之间。
14.根据权利要求11的方法,其中制造所述约束盘包括由铜制造所述约束盘。
15.根据权利要求14的方法,其中制造所述约束盘还包括制造圆形盘。
16.根据权利要求14的方法,其中制造所述约束盘的步骤还包括裁切所述约束盘的形状以符合所述基板上的可用空间。
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US12/020,561 US20090189289A1 (en) | 2008-01-27 | 2008-01-27 | Embedded constrainer discs for reliable stacked vias in electronic substrates |
US12/020,561 | 2008-01-27 | ||
PCT/EP2009/050585 WO2009124785A1 (en) | 2008-01-27 | 2009-01-20 | Embedded constrainer discs for reliable stacked vias in electronic substrates |
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US11270955B2 (en) * | 2018-11-30 | 2022-03-08 | Texas Instruments Incorporated | Package substrate with CTE matching barrier ring around microvias |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020034839A1 (en) * | 1998-10-16 | 2002-03-21 | Matsushita Electric Industrial Co., Ltd. | Multi-level circuit substrate, method for manufacturing same and method for adjusting a characteristic impedance therefor |
JP2005019730A (ja) * | 2003-06-26 | 2005-01-20 | Kyocera Corp | 配線基板およびそれを用いた電子装置 |
JP2005197720A (ja) * | 2004-01-07 | 2005-07-21 | Samsung Electronics Co Ltd | インピーダンス整合ホールを備える多層基板 |
JP2005251792A (ja) * | 2004-03-01 | 2005-09-15 | Fujitsu Ltd | 配線基板およびその製造方法 |
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JPH08172264A (ja) * | 1994-12-20 | 1996-07-02 | Hitachi Chem Co Ltd | 多層配線板および金属箔張り積層板の製造法 |
TW430935B (en) * | 1999-03-19 | 2001-04-21 | Ind Tech Res Inst | Frame type bonding pad structure having a low parasitic capacitance |
JP4052434B2 (ja) * | 2001-02-05 | 2008-02-27 | Tdk株式会社 | 多層基板及びその製造方法 |
JP2003163453A (ja) * | 2001-11-27 | 2003-06-06 | Matsushita Electric Works Ltd | 多層配線板の製造方法及び多層配線板 |
JP2005011883A (ja) | 2003-06-17 | 2005-01-13 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置および配線基板の製造方法 |
US7523545B2 (en) | 2006-04-19 | 2009-04-28 | Dynamic Details, Inc. | Methods of manufacturing printed circuit boards with stacked micro vias |
JP2008124398A (ja) * | 2006-11-15 | 2008-05-29 | Shinko Electric Ind Co Ltd | 半導体パッケージおよびその製造方法 |
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2008
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US20020034839A1 (en) * | 1998-10-16 | 2002-03-21 | Matsushita Electric Industrial Co., Ltd. | Multi-level circuit substrate, method for manufacturing same and method for adjusting a characteristic impedance therefor |
US6870264B2 (en) * | 1998-10-16 | 2005-03-22 | Matsushita Electric Industrial Co., Ltd. | Multi-level circuit substrate, method for manufacturing same and method for adjusting a characteristic impedance therefor |
JP2005019730A (ja) * | 2003-06-26 | 2005-01-20 | Kyocera Corp | 配線基板およびそれを用いた電子装置 |
JP2005197720A (ja) * | 2004-01-07 | 2005-07-21 | Samsung Electronics Co Ltd | インピーダンス整合ホールを備える多層基板 |
JP2005251792A (ja) * | 2004-03-01 | 2005-09-15 | Fujitsu Ltd | 配線基板およびその製造方法 |
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JP2011511436A (ja) | 2011-04-07 |
EP2238620A1 (en) | 2010-10-13 |
US20090189289A1 (en) | 2009-07-30 |
WO2009124785A1 (en) | 2009-10-15 |
TW200947657A (en) | 2009-11-16 |
KR20100111280A (ko) | 2010-10-14 |
KR101285030B1 (ko) | 2013-07-11 |
JP5182827B2 (ja) | 2013-04-17 |
EP2238620B1 (en) | 2011-08-24 |
ATE521989T1 (de) | 2011-09-15 |
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