CN105377390A - 包括叠置电子器件的电子组件 - Google Patents

包括叠置电子器件的电子组件 Download PDF

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Publication number
CN105377390A
CN105377390A CN201480003722.0A CN201480003722A CN105377390A CN 105377390 A CN105377390 A CN 105377390A CN 201480003722 A CN201480003722 A CN 201480003722A CN 105377390 A CN105377390 A CN 105377390A
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Prior art keywords
electronic device
electronic
building brick
chamber
packaging
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CN201480003722.0A
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CN105377390B (zh
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N·德什潘德
R·V·马哈詹
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Intel Corp
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Intel Corp
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Abstract

一种电子组件，所述电子组件包括第一电子器件。所述第一电子器件包括腔，所述腔延伸到所述第一电子器件的背侧中。所述电子组件还包括第二电子器件。所述第二电子器件在所述第一电子器件中的所述腔内安装到所述第一电子器件。在一些示例性形式的电子组件中，所述第一电子器件和所述第二电子器件中各自是管芯。应当指出的是，预期了所述电子组件的其它形式，其中，所述第一电子器件和第二电子器件中仅有一个是管芯。在一些形式的电子组件中，所述第二电子器件焊接到所述第一电子器件。

Description

包括叠置电子器件的电子组件
技术领域
本文所述的实施例总体上涉及电子组件，并且具体而言，涉及包括叠置电子器件的电子组件。
背景技术
与生产包括叠置电子器件(例如，管芯或芯片)的电子组件相关联的一个重要的考虑涉及从电子器件的叠置体中的底部电子器件有效地散热。另一个重要的考虑涉及处理包括穿硅过孔(TSV)的薄晶圆或管芯的能力，穿硅过孔用于随后将一个或多个额外电子器件叠置在薄晶圆或管芯上。
图1示出了现有技术电子封装10，其使用高热导率模制材料来从电子器件的叠置体中的底部电子器件散热。高热导率模制材料位于电子器件的叠置体中的最顶部电子器件与散热器之间。
图2示出了另一个现有技术电子封装20，其使用阶梯式集成散热器(IHS)来从电子器件的叠置体中的底部电子器件散热。使用阶梯式IHS常常提供对于在电子器件的叠置体中的最顶部电子器件与IHS之间的热分界面材料(TIM)粘合层的厚度的有限的控制。由于典型地与叠置电子器件相关联的容差问题而难以控制TIM粘合层的厚度。
图1和图2中所示的现有技术电子组件中解决热管理问题的方法之一是增大TIM粘合层的热导率。然而，单独增大TIM粘合层的热导率常常是不够的。
图1和图2中所示的现有技术电子组件中包括的电子器件的叠置体中的底部电子器件的厚度典型地约为100μm。底部电子器件的此最小厚度常常使得在包括叠置电子器件的电子组件的生产过程中安全且有效地处理底部电子器件是有问题的。
附图说明
图1示出了现有技术电子组件，其使用高热导率模制材料来从电子器件的叠置体中的底部电子器件散热。
图2示出了另一个现有技术的电子组件，其使用阶梯式集成散热器(IHS)来从电子器件的叠置体中的底部电子器件散热。
图3示出了示例性电子组件。
图4示出了在图3中所示的电子组件的一部分的放大图。
图5示出了示出在图3中所示的电子组件的另一种形式的一部分的放大图。
图6示出了示例性电子封装。
图7示出了在图6中所示的电子封装的一部分的放大图。
图8示出了示出在图6中所示的电子封装的另一种形式的一部分的放大图。
图9示出了图6中的电子封装，其中，该电子封装包括第三电子组件。
图10A-10D示出了用于在图6和图7中所示的电子封装的示例性封装工艺(即，组装流程)。
图11A-11D示出了用于在图8中所示的电子封装的示例性封装工艺(即，组装流程)。
图12是包括本文所述的电子组件和/或电子封装的电子装置的框图。
具体实施方式
以下描述和附图充分示出了具体实施例，以使得本领域技术人员能够实施它们。其它实施例可以包含结构、逻辑、电气、工艺以及其它变化。一些实施例的部分和特征可以包括在其它实施例的部分和特征中，或者代替它们。权利要求中阐述的实施例包含那些权利要求的全部可用的等效物。
如在本申请中使用的诸如“水平”的方位术语是相对于与晶圆或衬底的常规平面或表面平行的平面而定义的，而不管晶圆或衬底的取向如何。术语“垂直”指代与以上定义的水平垂直的方向。诸如“上”、“侧”(如“侧壁”中的)、“较高”、“较低”、“之上”、和“之下”是相对于在晶圆或衬底的顶部表面上的常规平面或表面而定义的，而不管晶圆或衬底的取向如何。
图3示出了示例性电子组件30。电子组件30包括第一电子器件31。第一电子器件31包括腔32，腔32延伸到第一电子器件31的背侧33中。
电子组件30还包括第二电子器件35。第二电子器件35在第一电子器件31中的腔32内安装到第一电子器件31。
在本文所示的示例中，第一电子器件31和第二电子器件35的各自是管芯。应当指出的是，预期了电子组件30的其它形式，其中，第一电子器件31和第二电子器件35中仅有一个是管芯。
图3示出了示例性电子组件30，其中，将第二电子器件35焊接到第一电子器件31。应当指出的是，第二电子器件35可以以其它方式附接到第一电子器件31。第二电子器件35附接到第一电子器件31的方式将部分取决于电子组件30的期望的结构和功能。
图4示出了在图3中所示的电子组件30的一部分的放大图。在图3和图4所示的示例性电子组件30中，第一电子器件31中的腔32部分地延伸通过第一电子器件31。在一些形式中，第一电子器件31包括电连接到第二电子器件35的穿硅过孔36。
在电子组件30的一些形式中，将腔32蚀刻到第一电子器件31中，以使得第二电子器件35在此蚀刻的腔32中适配，并将第二电子器件35电连接到第一电子器件31(例如，通过倒装芯片互连)。第一电子器件31的未蚀刻部分为用热的方式从第一电子器件31的蚀刻部分散热提供路径。另外，第一电子器件31的未蚀刻部分在电子组件30的制造期间为电子组件30提供机械刚度。
在图3和图4中所示的电子组件30的一些形式中，在将各自的第二电子器件叠置在第一电子器件31上之前，可以不必研磨包括多个第一电子器件31(例如，管芯)的晶圆的整个底部表面。相反，在晶圆中仅对晶圆中的需要将顶部管芯适配到腔内的部分进行蚀刻。应当指出的是，可以在蚀刻的腔中生成针对基于TSV(或非TSV)的互连的多种设计，以便将第二电子器件35附接在晶圆上。随后可以用环氧树脂(或一些其它适当的材料)填充围绕各自第二电子器件35的互连和腔。
应当指出的是，本文所述的电子组件30的结构可以不增大电子组件30的总高度，因为第一电子器件31的未蚀刻部分的高度是更可控制的。另外，与使用阶梯式IHS或高热导率聚合物相比，第一电子器件31的未蚀刻部分是更好的热导体，并且改进了从第一电子器件31的散热。第一电子器件31的未蚀刻部分还可以为第一电子器件31提供结构刚度，从而使得在电子组件30的制造期间更易于处理第一电子器件31。
应当指出的是，本文所述的电子组件30的结构可以允许将第一电子器件31中的腔31的顶部表面用作硬停(hardstop)，所述硬停用于对可以叠置到第一电子器件31上的其它电子器件的准确的Z方向定位。另外，电子组件可以在电子器件的叠置体的顶部上提供平坦表面，以用于随后对IHS的附接。在电子组件的一些形式中，电子器件的叠置体中的顶部电子器件可以包含有源管芯或仅包含集成无源器件，诸如包括使用硅构造的磁芯电感器的电感器或者包括MIM(金属-绝缘体-金属)电容器的电容器，用以改进功率输送性能。
图5示出了示出在图3中所示的电子组件30的另一种形式的一部分的放大图。在图5中所示的示例性电子组件30中，第一电子器件31中的腔32延伸通过第一电子器件31的一部分。第一电子器件31可以包括在第一电子器件31的前侧38上的内插件37。可以将第一电子器件31安装到内插件37和/或第二电子器件35。在内插件37的一些形式中，第一电子器件31是具有充当内插件的前侧金属互连(即，内插件37是电子器件31的部分)的无源器件。
应当指出的是，本文所述的电子组件30的结构可以允许芯片的2.5D叠置，而不必在第一电子器件中制造TSV。另外，电子组件可以用于多种3D以及2.5D叠置方案。
图6示出了示例性电子封装60。电子封装60包括衬底69和安装在衬底69上的第一电子器件61。第一电子器件61包括腔62，腔62延伸到第一电子器件61的背侧63中。
电子封装60还包括第二电子器件65。第二电子器件65在第一电子器件61中的腔62内安装到第一电子器件61。
图6示出了示例性电子封装，其中，将第二电子器件65焊接到第一电子器件61。应当指出的是，第二电子器件65可以以其它方式连接到第一电子器件61。第二电子器件65连接到第一电子器件61的方式部分地取决于电子封装60的期望的结构和功能。
图7示出了在图6中所示的电子封装60的一部分的放大图。在图6和图7所示的示例性电子组件60中，第一电子器件61中的腔62部分地延伸通过第一电子器件61。在一些形式中，第一电子器件61包括穿硅过孔66，穿硅过孔66电连接到第二电子器件65和/或衬底69。
图8示出了示出在图6中所示的电子封装60的另一种形式的一部分的放大图。在图8中所示的示例性电子封装60中，第一电子器件61中的腔62延伸通过第一电子器件61的一部分。第一电子器件61可以包括在第一电子器件61的前侧68上的内插件67。可以将第一电子器件61安装到内插件67和/或第二电子器件65。
内插件67和衬底69可以由硅构成。在电子封装60的其它示例性形式中，内插件67和衬底69中的至少一个是玻璃。用于内插件67和衬底69的其它示例性材料包括但不限于硅、玻璃、绝缘体上硅、碳化硅(SiC)、砷化镓、有机衬底和层合体等。应当指出的是，内插件67和衬底69可以是相同的材料或不同的材料。应当指出的是，当前已知或未来会发现的任何技术都可以用于将内插件67附接到衬底69并且构成在内插件67与衬底69之间的电连接。
图9示出了图6的电子封装60，其中，电子封装60包括第三电子组件71。在本文所示的示例中，第一电子器件61、第二电子器件65和第三电子器件71各自是管芯。应当指出的是，预期了电子封装60的其它形式，其中，第一电子器件61、第二电子器件65和第三电子器件71中的仅有一个或两个是管芯。
第三电子器件71可以安装到第一电子器件61和/或第二电子器件65。另外，尽管图9仅示出了第一电子器件61、第二电子器件65和第三电子器件71，但取决于电子封装60的总体结构，另外的电子器件可以附接到第一电子器件61、第二电子器件65和第三电子器件71中的任意一个。
例如，第三电子器件71可以焊接到第一电子器件61和第二电子器件65的至少一个。应当指出的是，第三电子器件71可以以其它方式附接到第一电子器件61和/或第二电子器件65。第三电子器件71附接到第一电子器件61和/或第二电子器件65的方式将部分地取决于电子封装60的期望的结构和功能。
图10A-10D示出了用于在图6和图7中所示的电子封装60的示例性封装工艺(即，组装流程)。
图11A-11D示出了用于在图8中所示的电子封装60的示例性封装工艺(即，组装流程)。
本文所述的电子组件30和电子封装60可易于适合制造，尤其是当电子组件30和电子封装60是电子器件(例如，管芯)的3D或2.5D叠置体的部分时。另外，本文所述的电子组件30和电子封装60可以从是电子器件的叠置体的部分的底部电子器件有效地散热。
图12是包含至少一个本文所述的电子组件30和/或电子封装60的电子装置1200的框图。电子装置1200仅是其中可以使用本文所述的电子组件30和/或电子封装60的形式的电子装置的一个示例。电子装置1200的示例包括但不限于个人计算机、平板计算机、移动电话、游戏机、MP3或其它数字音乐播放器等。在此示例中，电子装置1200包括数据处理系统，所述数据处理系统包括用以耦合电子装置1200的各个部件的系统总线1202。系统总线1202提供在电子装置1200的各个部件之中的通信链路，并且可以实施为单条总线、总线组合或以任何其它适合的方式。
本文所述的电子组件1210可以耦合到系统总线1202。电子组件1210可以包括任何电路或电路组合。在一个实施例中，电子组件1210包括可以是任何类型的处理器1212。本文所用的“处理器”意指任何类型的运算电路，诸如但不限于微处理器、微控制器、复杂指令集运算(CISC)微处理器、精简指令集运算(RISC)微处理器、超长指令字(VLIW)微处理器、图形处理器、数字信号处理器(DSP)、多核处理器或任何其它类型的处理器或处理电路。
可以包括在电子组件1210中的其它类型的电路是定制电路、专用集成电路(ASIC)等，诸如例如在如移动电话、平板计算机、笔记本计算机、双向无线电设备和类似电子系统的无线设备中使用的一个或多个电路(诸如，通信电路1214)。IC可以执行任何其它类型的功能。
电子装置1200还可以包括外部存储器1220，外部存储器1220继而可以包括适合于特定应用的一个或多个存储元件，诸如以随机存取存储器(RAM)形式的主存储器1222、一个或多个硬盘驱动器1224、和/或一个或多个驱动器，所述一个或多个驱动器处理可移动介质1226，诸如光盘(CD)、闪存卡、数字视频盘(DVD)等。
电子装置1200还可以包括显示设备1216、一个或多个扬声器1218和键盘和/或控制器1230，控制器1230可以包括鼠标、轨迹球、触摸屏、语音识别设备、或允许系统用户将信息输入到电子装置1200中并从电子装置1200接收信息的任何其它设备。
为了更好地示出本文公开的方法和装置，在此提供实施例的非限制性列表：
示例1包括电子组件，所述电子组件包括第一电子器件。所述第一电子器件包括腔，所述腔延伸到所述第一电子器件的背侧中。第二电子器件在所述第一电子器件中的所述腔内安装到所述第一电子器件。
示例2包括示例1的电子组件，其中，所述第一电子器件和所述第二电子器件中的至少一个是管芯。
示例3包括示例1-2中的任意一个的电子组件，其中，所述第二电子器件焊接到所述第一电子器件。
示例4包括示例1-3中的任意一个的电子组件，其中，所述第一电子器件中的所述腔部分地延伸通过所述第一电子器件。
示例5包括示例1-4中的任意一个的电子组件，其中，所述第一电子器件包括在所述第一电子器件的前侧上的内插件，并且其中，所述第一电子器件中的所述腔延伸通过所述第一电子器件而到达所述内插件。
示例6包括示例5的电子组件，其中，所述第二电子器件安装到所述内插件。
示例7包括示例1-6中的任意一个的电子组件，其中，所述第一电子器件包括穿硅过孔，所述穿硅过孔电连接到所述第二电子器件。
示例8包括一种电子封装，所述电子封装包括衬底和安装到所述衬底上的第一电子器件。第一电子器件包括腔，所述腔延伸到所述第一电子器件的背侧中。第二电子器件在所述第一电子器件中的所述腔内安装到所述第一电子器件。
示例9包括示例8的电子封装，其中，所述第一电子器件包括穿硅过孔，所述穿硅过孔将所述第二电子器件电连接到所述衬底。
示例10包括示例8-9中的任意一个的电子封装，并且还包括第三电子器件，所述第三电子器件安装到所述第一电子器件和所述第二电子器件中的至少一个。
示例11包括示例10的电子封装，其中，所述第三电子器件安装到所述第一电子器件和所述第二电子器件。
示例12包括示例10-11中的任意一个的电子封装，其中，所述第三电子器件焊接到所述第一电子器件和第二电子器件中的至少一个。
示例13包括示例10-12中的任意一个的电子封装，其中，所述第一电子器件、所述第二电子器件和所述第三电子器件中的至少一个是管芯。
示例14包括示例8-13中的任意一个的电子封装，其中，所述第二电子器件焊接到所述第一电子器件。
示例15包括示例8-14中的任意一个的电子封装，其中，所述第一电子器件中的所述腔部分地延伸通过所述第一电子器件。
示例16包括示例8-14中的任意一个的电子封装，其中，所述第一电子器件包括在所述第一电子器件的前侧上的内插件，并且其中，所述第一电子器件中的所述腔延伸通过所述第一电子器件而到达所述内插件。
示例17包括示例8-16中的任意一个的电子封装，其中，所述第一电子器件包括穿硅过孔，所述穿硅过孔将所述第一电子器件电连接到所述第二电子器件。
示例18包括一种电子封装，所述电子封装包括衬底和安装到所述衬底上的第一电子器件。所述第一电子器件焊接到所述衬底并且包括腔，所述腔延伸到所述第一电子器件的背侧中。第二电子器件在所述第一电子器件中的所述腔内焊接到所述第一电子器件，并且第三电子器件焊接到所述第一电子器件和所述第二电子器件中的至少一个。
示例19包括示例18的电子封装，其中，所述第一电子器件、所述第二电子器件和所述第三电子器件中的至少一个是管芯。
示例20包括示例18-19的电子封装，其中，所述第一电子器件中的所述腔部分地延伸通过所述第一电子器件。
在具体实施方式中将部分地阐述本电子组件和电子封装的这些及其它示例和特征。
本概述旨在提供当前主题的非限制性示例。并非旨在提供排他性或穷举性解释。包括了详细说明以便提供关于本文所述的电子组件30和/或电子封装60的进一步信息。
以上的具体实施方式包括对附图的参考，附图构成具体实施方式的一部分。附图示例性地示出了其中可以实施本发明的具体实施例。这些实施例在本文也被称为“示例”。这种示例可以包括除了所示或所述的要素以外的要素。然而，本发明人还预期了其中仅提供了所示或所述的那些要素的示例。此外，相对于特定示例(或者其一个或多个方面)或者相对于本文所示或所述的其它示例(或者其一个或多个方面)，本发明人还预期了使用所示或所述的那些要素(或者其一个或多个方面)的任意组合或排列的示例。
在本文件中，如同通常专利文件中一样地使用了术语“一”或“一个”，以包括一个或多于一个，与“至少一个”或“一个或多个”的任何其它实例或使用无关。在本文件中，将术语“或者”用于指代非排他性的或者，以使得“A或者B”包括“A但不是B”、“B但不是A”和“A和B”，除非另外指示。在本文件中，将术语“包括”和“在其中”用作各自术语“包含”和“其中”的简明英语的等效物。此外，在以下权利要求中，术语“包含”和“包括”是开放式的，即，包括除了在权利要求中这个术语之后所列出的以外的要素的系统、设备、制品、组分、形成或工艺仍视为落入该权利要求的范围内。此外，在以下权利要求中，术语“第一”、“第二”、和“第三”等仅用作标记，而并非旨在对其对象强加编号要求。
以上说明旨在是示例性而非限制性的。例如，上述的示例(或者其一个或多个方案)可以彼此结合地使用。诸如，本领域技术人员一旦回顾了以上描述后就可以使用其它实施例。
提供摘要以符合37C.F.R.§1.72(b)，与允许读者迅速确定本技术公开内容的本质。应理解本摘要并不用于解释或限定权利要求的范围或含义。
此外，在以上的具体实施方式中，多个特征可以分组在一起以简化本公开内容。这不应解释为意指未要求保护的所公开的特征对于任何权利要求是必不可少的。相反，在少于特定的所公开的实施例的全部特征的情况下，创造性的主题也可以存在。因而以下权利要求在此包含在具体实施方式中，其中每一个权利要求都独立作为单独的实施例，并且预期了这种实施例可以以多种组合或排列彼此结合。本发明的范围应参考所附权利要求连同这些权利要求被赋予的等效方案的全部范围来确定。

Claims (20)

1.一种电子组件，包括：
第一电子器件，所述第一电子器件包括腔，所述腔延伸到所述第一电子器件的背侧中；以及
第二电子器件，所述第二电子器件在所述第一电子器件中的所述腔内安装到所述第一电子器件。
2.根据权利要求1所述的电子组件，其中，所述第一电子器件和所述第二电子器件中的至少一个是管芯。
3.根据权利要求1所述的电子组件，其中，所述第二电子器件焊接到所述第一电子器件。
4.根据权利要求1所述的电子组件，其中，所述第一电子器件中的所述腔部分地延伸通过所述第一电子器件。
5.根据权利要求1所述的电子组件，其中，所述第一电子器件包括在所述第一电子器件的前侧上的内插件，并且其中，所述第一电子器件中的所述腔延伸通过所述第一电子器件而到达所述内插件。
6.根据权利要求5所述的电子组件，其中，所述第二电子器件安装到所述内插件。
7.根据权利要求1所述的电子组件，其中，所述第一电子器件包括穿硅过孔，所述穿硅过孔电连接到所述第二电子器件。
8.一种电子封装，包括：
衬底；
第一电子器件，所述第一电子器件安装在所述衬底上，所述第一电子器件包括腔，所述腔延伸到所述第一电子器件的背侧中；以及
第二电子器件，所述第二电子器件在所述第一电子器件中的所述腔内安装到所述第一电子器件。
9.根据权利要求8所述的电子封装，其中，所述第一电子器件包括穿硅过孔，所述穿硅过孔将所述第二电子器件电连接到所述衬底。
10.根据权利要求8所述的电子封装，还包括第三电子器件，所述第三电子器件安装到所述第一电子器件和所述第二电子器件中的至少一个。
11.根据权利要求10所述的电子封装，其中，所述第三电子器件安装到所述第一电子器件和所述第二电子器件。
12.根据权利要求10所述的电子封装，其中，所述第三电子器件焊接到所述第一电子器件和所述第二电子器件中的至少一个。
13.根据权利要求12所述的电子封装，其中，所述第一电子器件、所述第二电子器件和所述第三电子器件中的至少一个是管芯。
14.根据权利要求8所述的电子封装，其中，所述第二电子器件焊接到所述第一电子器件。
15.根据权利要求8所述的电子封装，其中，所述第一电子器件中的所述腔部分地延伸通过所述第一电子器件。
16.根据权利要求8所述的电子封装，其中，所述第一电子器件包括在所述第一电子器件的前侧上的内插件，并且其中，所述第一电子器件中的所述腔延伸通过所述第一电子器件而到达所述内插件。
17.根据权利要求8所述的电子封装，其中，所述第一电子器件包括穿硅过孔，所述穿硅过孔将所述第一电子器件电连接到所述第二电子器件。
18.一种电子封装，包括：
衬底；
第一电子器件，所述第一电子器件焊接到所述衬底，所述第一电子器件包括腔，所述腔延伸到所述第一电子器件的背侧中；
第二电子器件，所述第二电子器件在所述第一电子器件中的所述腔内焊接到所述第一电子器件；以及
第三电子器件，所述第三电子器件焊接到所述第一电子器件和所述第二电子器件中的至少一个。
19.根据权利要求18所述的电子封装，其中，所述第一电子器件、所述第二电子器件和所述第三电子器件中的至少一个是管芯。
20.根据权利要求18所述的电子封装，其中，所述第一电子器件中的所述腔部分地延伸通过所述第一电子器件。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9941246B2 (en) 2014-07-02 2018-04-10 Intel Corporation Electronic assembly that includes stacked electronic devices

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9583426B2 (en) 2014-11-05 2017-02-28 Invensas Corporation Multi-layer substrates suitable for interconnection between circuit modules
US10283492B2 (en) * 2015-06-23 2019-05-07 Invensas Corporation Laminated interposers and packages with embedded trace interconnects

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128882A1 (en) * 2006-12-05 2008-06-05 Samsung Electronics Co., Ltd. Chip stack package and method of manufacturing the same
US20100102428A1 (en) * 2008-10-28 2010-04-29 Samsung Electronics Co., Ltd Semiconductor package
CN102106194A (zh) * 2006-12-14 2011-06-22 英特尔公司 具有凹嵌的器件的陶瓷封装衬底
US20130181354A1 (en) * 2012-01-12 2013-07-18 Broadcom Corporation Semiconductor Interposer Having a Cavity for Intra-Interposer Die
CN103855129A (zh) * 2012-12-06 2014-06-11 德州仪器公司 半导体装置及用于制作半导体装置的方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100234719B1 (ko) * 1997-03-14 1999-12-15 김영환 에리어 어레이 패키지 및 그 제조방법
US7098070B2 (en) * 2004-11-16 2006-08-29 International Business Machines Corporation Device and method for fabricating double-sided SOI wafer scale package with through via connections
EP2033282B1 (en) * 2006-06-16 2012-10-31 Russian limited liability company "Connector Optics" Optoelectronic device for high-speed data transfer
SG149724A1 (en) 2007-07-24 2009-02-27 Micron Technology Inc Semicoductor dies with recesses, associated leadframes, and associated systems and methods
TWI335059B (en) * 2007-07-31 2010-12-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same
US9875911B2 (en) 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8519537B2 (en) 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
KR101205144B1 (ko) 2010-06-28 2012-11-26 현대제철 주식회사 건축구조용 ｈ형강 및 그 제조방법
KR20120006770A (ko) * 2010-07-13 2012-01-19 주식회사 하이닉스반도체 테스트 모듈 및 이를 이용한 스택 패키지의 제조방법
US8598695B2 (en) * 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
KR101163899B1 (ko) 2010-08-05 2012-07-09 권대식 분수장치
TWI445104B (zh) * 2010-08-25 2014-07-11 Advanced Semiconductor Eng 半導體封裝結構及其製程
US9111912B2 (en) * 2013-05-30 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
EP3164886A4 (en) 2014-07-02 2018-06-20 Intel Corporation Electronic assembly that includes stacked electronic devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128882A1 (en) * 2006-12-05 2008-06-05 Samsung Electronics Co., Ltd. Chip stack package and method of manufacturing the same
CN102106194A (zh) * 2006-12-14 2011-06-22 英特尔公司 具有凹嵌的器件的陶瓷封装衬底
US20100102428A1 (en) * 2008-10-28 2010-04-29 Samsung Electronics Co., Ltd Semiconductor package
US20130181354A1 (en) * 2012-01-12 2013-07-18 Broadcom Corporation Semiconductor Interposer Having a Cavity for Intra-Interposer Die
CN103855129A (zh) * 2012-12-06 2014-06-11 德州仪器公司 半导体装置及用于制作半导体装置的方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9941246B2 (en) 2014-07-02 2018-04-10 Intel Corporation Electronic assembly that includes stacked electronic devices

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