TWI624910B - 包括堆疊電子裝置的電子總成 - Google Patents

包括堆疊電子裝置的電子總成 Download PDF

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Publication number
TWI624910B
TWI624910B TW104117626A TW104117626A TWI624910B TW I624910 B TWI624910 B TW I624910B TW 104117626 A TW104117626 A TW 104117626A TW 104117626 A TW104117626 A TW 104117626A TW I624910 B TWI624910 B TW I624910B
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Taiwan
Prior art keywords
integrated circuit
circuit die
electronic device
electronic
sided cavity
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TW104117626A
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English (en)
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TW201613038A (en
Inventor
尼亭 戴斯潘迪
拉維Ｖ 馬哈吉
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美商英特爾公司
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Publication of TW201613038A publication Critical patent/TW201613038A/zh
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Abstract

一電子總成包括一第一電子裝置。該第一電子裝置包括一延伸至該第一電子裝置之背側的空穴。該電子總成更包括一第二電子裝置。該第二電子裝置被安裝至該第一電子裝置位在該第一電子裝置中的空穴之內。在該電子總成的一些範例態樣中，該第一電子裝置與該第二電子裝置各是為一晶粒。應要注意的是該電子總成的其他態樣是被考量，其中，該第一電子裝置與該第二電子裝置中之僅一者是為一晶粒。在該電子總成的一些態樣中，該第二電子裝置被銲接至該第一電子裝置。

Description

包括堆疊電子裝置的電子總成 發明領域
於此中所述的實施例大致上係有關於電子總成，更特別地，係有關於包括堆疊電子裝置的電子總成。
發明背景
與生產包括堆疊電子裝置(例如，晶粒或晶片)之電子總成相關聯的一個重要考量係關於有效地把熱從在堆疊電子裝置中的底部電子裝置散發出來。另一個重要考量係關於處理包括貫穿矽通孔(TSVs)之薄晶圓或晶粒的能力，該等貫穿矽通孔是用於後續一個或多個其他電子裝置到該等薄晶圓或晶粒上的堆疊。
圖1顯示一使用高導熱鑄模材料來把熱從在堆疊電子裝置中之底部電子裝置散發出來的習知電子封裝體10。該高導熱鑄模材料被定位在堆疊電子裝置中的最頂部電子裝置與一散熱器之間。
圖2顯示使用一梯狀(stepped)整合式散熱器(IHS)來把熱從在堆疊電子裝置中之底部電子裝置散發出來的另一個習知電子封裝體20。使用一梯狀IHS經常提供位於在堆 疊電子裝置中之最頂部電子裝置與該IHS之間之熱界面材料(TIM)黏著層之厚度的受限控制。該TIM黏著層的厚度由於典型地與堆疊電子裝置相關聯的公差問題而難以控制。
熱管理問題是針對在圖1與2中所示之習知電子總成的其中一種方式是為提升該TIM黏著層的熱傳導性。然而，提升該TIM黏著層的熱傳導性通常不是單獨合適的。
在被包括於在圖1和2中所示之習知電子總成內之堆疊電子裝置中之底部電子裝置的厚度典型地是為大約100um。該底部電子裝置的這最小厚度通常使得在包括疊堆式電子裝置之電子總成的生產期間要安全地且有效率地處理該底部電子裝置是有問題的。
依據本發明之一實施例，係特地提出一種電子總成，其包含：一第一電子裝置，其包括延伸至該第一電子裝置之一背側的一空穴；以及一第二電子裝置，其安裝至該第一電子裝置位於在該第一電子裝置中的該空穴之內。
10‧‧‧電子封裝體
20‧‧‧電子封裝體
30‧‧‧電子總成
31‧‧‧第一電子裝置
32‧‧‧空穴
33‧‧‧背面
35‧‧‧第二電子裝置
36‧‧‧貫穿矽通孔
37‧‧‧中介層
38‧‧‧前側
60‧‧‧電子封裝體
61‧‧‧第一電子裝置
62‧‧‧空穴
63‧‧‧背側
65‧‧‧第二電子裝置
66‧‧‧貫穿矽通孔
67‧‧‧中介層
68‧‧‧前側
69‧‧‧基體
71‧‧‧第三電子裝置
1200‧‧‧電子裝置
1202‧‧‧系統匯流排
1210‧‧‧電子總成
1212‧‧‧處理器
1214‧‧‧通訊電路
1216‧‧‧顯示器裝置
1218‧‧‧揚聲器
1220‧‧‧外部記憶體
1222‧‧‧主記憶體
1224‧‧‧硬碟機
1226‧‧‧可移除媒體
1230‧‧‧控制器
圖1顯示一使用高導熱鑄模材料來把熱從在堆疊電子裝置中之底部電子裝置散發出來的習知電子總成。
圖2顯示使用一梯狀(stepped)整合式散熱器(IHS)來把熱從在堆疊電子裝置中之底部電子裝置散發出來的另一個習知電子封裝體。
圖3描繪一範例電子總成。
圖4顯示在圖3中所示之電子總成之一部份的放大圖。
圖5顯示一描繪在圖3中所示之電子總成之另一態樣之一部份的放大圖。
圖6描繪一範例電子封裝體。
圖7顯示在圖6中所示之電子封裝體之一部份的放大圖。
圖8顯示一描繪在圖6中所示之電子封裝體之另一態樣之一部份的放大圖。
圖9顯示圖6的電子封裝體，其中，該電子封裝體包括一第三電子組件。
圖10A-10D顯示一用於在圖6和7中所描繪之電子封裝體的範例封裝製程(即，組裝流程)。
圖11A-11D顯示一用於在圖8中所描繪之電子封裝體的範例封裝製程(即，組裝流程)。
圖12是為一電子裝置的方塊圖，該電子裝置包括於此中所述的電子總成及/或電子封裝體。
較佳實施例之詳細說明
後面的描述和該等圖式充份地描繪具體實施例以使得熟知此項技術之人仕能夠實施它們。其他的實施例可以合併結構、邏輯、電氣、製程、及其他改變。一些實施例的部份與特徵可以被包括在，或者，替代，其他實施例的那些。在申請專利範圍中所陳述的實施例涵蓋那些申 請專利範圍的所有可得到等效物。
如在這申請案中所使用的方位術語，像是”水平”般，是相對於一與習知平面或晶圓或基體之表面平行的平面來被界定，不管該晶圓或基體的方位。該術語”垂直”是指與如上所述之水平垂直的方向。介系詞”在上面”、”側面”(如同在”側壁”)、”較高”、”較低”、”在上面”、和”在下面”是相對於該習知平面或者位在該晶圓或基體之上表面上的表面來被界定，不管該晶圓或基體的方位。
圖3顯示一範例電子總成30。該電子總成30包括一第一電子裝置31。該第一電子裝置31包括一空穴32，該空穴32延伸至該第一電子裝置31的背面33。
該電子總成30更包括一第二電子裝置35。該第二電子裝置35被安裝到該第一電子裝置31位在該在該第一電子裝置31中的空穴32之內。
於在此中所示的範例中，該第一電子裝置31與該第二電子裝置35各是為一晶粒。應要注意的是該電子總成30的其他態樣是被考量，其中，該第一電子裝置31與該第二電子裝置35中之僅一者是為一晶粒。
圖3顯示一範例電子總成30，在其中，該第二電子裝置35是被銲接到該第一電子裝置31。應要注意的是該第二電子裝置35能夠以其他方式被連接到該第一電子裝置31。該第二電子裝置35被連接至該第一電子裝置31的方式將會部份端視該電子總成30的希望結構與功能而定。
圖4顯示在圖3中所示之電子總成30之一部份的 放大圖。在圖3與4中所示的範例電子總成30中，於該第一電子裝置31內的空穴32部份地延伸通過該第一電子裝置31。在一些態樣中，該第一電子裝置31包括電氣地連接到該第二電子裝置35的貫穿矽通孔36。
在電子總成30的一些態樣中，該空穴32被蝕刻至該第一電子裝置31內以致於該第二電子裝置35裝配在這蝕刻空穴32內而且是把該第二電子裝置35電氣地連接至該第一電子裝置31(例如，經由覆晶式互連接)。該第一電子裝置31的未被蝕刻部份提供一個用於把熱從該第一電子裝置31之蝕刻部份散發出來的路徑。此外，該第一電子裝置31的未蝕刻部份在該電子總成30的製造期間提供該電子總成30機械剛性。
在圖3與4中所示之電子總成30的一些態樣中，在對應的第二電子裝置被堆疊到該等第一電子裝置31上之前研磨包括數個第一電子裝置31(例如，晶粒)之晶圓的整個底面不是必要的。取而代之，僅該晶圓之該在它那裡必須裝配最頂部晶粒在空穴之內的部份是被蝕刻在該晶圓。應要注意的是TSVs(或非-TSV)基互連線的各種設計可以被產生在該等蝕刻空穴內俾可把該等第二電子裝置35連接到該晶圓上。包圍對應之第二電子裝置35的互連線與空穴然後是會以環氧樹脂(或者一些其他適當材料)填充。
應要注意的是於此中所述之電子總成30的結構不會增加該電子總成30的整體高度因為該第一電子裝置31之未蝕刻部份的高度是更可控制。此外，該第一電子裝置 31的未蝕刻部份是為較佳的熱導體並且與使用梯狀IHS或高傳導聚合物比較起來提升熱從該第一電子裝置31散出。該第一電子裝置31的未蝕刻部份也可以提供該第一電子裝置31結構剛性藉此使得在電子總成30的製造期間該第一電子裝置31的處理更容易。
應要注意的是於此中所述之電子總成30的結構會允許在該第一電子裝置31中之空穴32的上表面被使用作為用於其他能夠被堆疊到該第一電子裝置31上之電子裝置之精準Z定位的硬擋止。此外，該等電子總成可以提供一平表面在堆疊電子裝置的頂部上以供後續IHS的連接用。在該等電子總成的一些態樣中，於堆疊電子裝置中的頂部電子裝置可以包含一主動晶粒或者僅整合式被動元件，像包括使用矽建立之磁芯電感器的電感器或包括MIM(金屬-絕緣體-金屬)的電容器般，俾改進電力傳輸性能。
圖5顯示一描繪在圖3中所示之電子總成30之另一態樣之一部份的放大圖。在圖5中所示的範例電子總成30中，於該第一電子裝置31中的空穴32延伸通過該第一電子裝置31的一部份。該第一電子裝置31可以包括一中介層37在該第一電子裝置31的前側38上。該第一電子裝置31可以被安裝到該中介層37及/或該第二電子裝置35。在該中介層37的一些態樣中，該第一電子裝置31是為一被動裝置，其前側金屬互連線作用如中介層(即，中介層37是為電子裝置31的部份)。
應要注意的是於此中所述之電子總成30的結構 在不必於該第一電子裝置中製造TSVs之下會允許晶片的2.5D堆疊。此外，該等電子總成可以被使用於各種3D以及2.5D堆疊方案。
圖6顯示一範例電子封裝體60。該電子封裝體60包括一基體69及一安裝於該基體69上的第一電子裝置61。該第一電子裝置61包括一延伸至該第一電子裝置61之背側63內的空穴62。
該電子封裝體60更包括一第二電子裝置65。該第二電子裝置65被安裝到該第一電子裝置61位於該在該第一電子裝置61內的空穴62之內。
圖6顯示一範例電子封裝體，其中，該第二電子裝置65被銲接到該第一電子裝置61。應要注意的是該第二電子裝置65能夠以其他方式被連接到該第一電子裝置61。該第二電子裝置65被連接到該第一電子裝置61的方式將會部份端視該電子封裝體60的希望結構與功能而定。
圖7顯示在圖6中所示之電子封裝體60之一部份的放大圖。在圖6與7中所示的範例電子封裝體60中，在該第一電子裝置61中的空穴62部份地延伸通過該第一電子裝置61。在一些態樣中，該第一電子裝置61包括電氣連接到該第二電子裝置65及/或該基體69的貫穿矽通孔66。
圖8顯示一描繪在圖6中所示之電子封裝體60之另一態樣之一部份的放大圖。在圖8中所示的範例電子封裝體60中，於該第一電子裝置61中的空穴62延伸通過該第一電子裝置61的一部份。該第一電子裝置61可以包括一中介 層67在該第一電子裝置61的前側68上。該第一電子裝置61可以被安裝到該中介層67及/或該第二電子裝置65。
該中介層67與該基體69可以是由矽形成。在該電子封裝體60的又另一範例態樣中，該基體69與該中介層67中之至少一者是為玻璃。該中介層67與該基體69的其他範例材料包括，但不限於，矽、玻璃、矽在絕緣體上、碳化矽(SiC)、砷化鎵、有機基體與疊層等等。應要注意的是該中介層67與該基體69可以是相同的材料或者是不同的材料。應要注意的是目前已知，或者在未來被發現的任何技術是可以被用來把該中介層67連接到該基體69及形成在該中介層67與該基體69之間的電氣連接。
圖9顯示圖6的電子封裝體60，其中，該電子封裝體60包括一第三電子裝置71。於此中所示的範例中，該第一、第二和第三電子裝置61,65,71各是為一晶粒。應要注意的是該電子封裝體60之第一、第二與第三電子裝置61,65,71中之僅一者或兩者是為晶粒的其他態樣是被考量的。
該第三電子裝置71可以被安裝到該第一電子裝置61及/或該第二電子裝置65。此外，雖然圖9僅顯示第一、第二和第三電子裝置61,65,71，端視該電子封裝體60的整體結構而定額外的電子裝置是可以被連接到該第一、第二和第三電子裝置61,65,71中之任一者。
作為一範例，該第三電子裝置71可以被銲接到該第一電子裝置61與該第二電子裝置65中之至少一者。應要注意的是該第三電子裝置71可以以其他方式連接到該第一 及/或第二電子裝置61,65。該第三電子裝置71被連接到該第一及/或第二電子裝置61,65的形式將會部份端視該電子封裝體60的希望結構及功能而定。
圖10A-10D顯示在圖6和7中所描繪之電子封裝體60的範例封裝製程(即，組裝流程)。
圖11A-11D顯示在圖8中所描繪之電子封裝體60的範例封裝製程(即，組裝流程)。
於此中所述的電子總成30和電子封裝體60能夠容易適用於生產，尤其是當該等電子總成30與該等電子封裝體60是為3D或2.5D堆疊電子裝置(例如，晶粒)的部份時。此外，於此中所述的電子總成30和電子封裝體60能夠有效地把熱從是為堆疊電子裝置之部份的底層電子裝置散發出來。
圖12是為一合併於此中所述之電子總成30及/或電子封裝體60中之至少一者之電子裝置1200的方塊圖。電子裝置1200僅是為一可以使用於此中所述之電子總成30及/或電子封裝體60之態樣之電子裝置的一個範例。一電子裝置1200的範例包括，但不限於，個人電腦、平板電腦、行動電話、遊戲裝置、MP3或其他數位音樂播放器等等。在這範例中，電子裝置1200包含一包括一耦接電子裝置1200之各種組件之系統匯流排1202的資料處理系統。系統匯流排1202提供在該電子裝置1200之各種組件之間的通訊鏈結並且可以被實現如一單一匯流排、實現如匯流排的組合、或者實現成任何其他適當的形式。
於此中所述的一電子總成1210可以被耦接到系統匯流排1202。該電子總成1210可以包括任何電路或者電路的組合。在一實施例中，該電子總成1210包括一能夠是為任何類型的處理器1212。如於此中所使用，"處理器"意指任何類型的計算電路，像是但不限於微處理器、微控制器、複雜指令集計算(CISC)微處理器、精簡指令集計算(RISC)微處理器、非常長指令字(VLIW)微處理器、圖形處理器、數位訊號處理器(DSP)、多核心處理器、或任何其他類型的處理器或處理電路般。
可以被包括於電子總成1210內之其他類型的電路是為一客製化電路、一特殊用途積體電路(ASIC)等等，像是，例如，用於像行動電話之無線裝置、平板電腦、膝上型電腦、雙向無線電、及相類似之電子系統的一個或多個電路(諸如一通訊電路1214般)。該IC能夠執行任何其他類型的功能。
電子裝置1200也可以包括一外部記憶體1220，其可以包括一個或多個適於特別用途的記憶體元件，像是一採用隨機存取記憶體(RAM)之形式的主記憶體1222、一個或多個硬碟機1224、及/或一個或多個處理像是光碟(CD)、快閃記憶體卡、數位視頻碟(DVD)等等般之可移除媒體1226的驅動器般。
該電子裝置1200也可以包括一顯示器裝置1216、一個或多個揚聲器1218、及一鍵盤及/或控制器1230，其可以包括一滑鼠、軌跡球、觸控螢幕、語音辨識裝置、或任 何其他允許系統使用者輸入資訊至該電子裝置1200及從該電子裝置1200接收資訊的裝置。
為了更佳描繪於此中所述的方法與裝置，一非限制性實施例的列表是被提供在此。
範例1包括一個包括一第一電子裝置的電子總成。該第一電子裝置包括一延伸至該第一電子裝置之背側內的空穴。一第二電子裝置被安裝到該第一電子裝置位在該第一電子裝置中的空穴之內。
範例2包括範例1的電子總成，其中，該第一電子裝置與該第二電子裝置中之至少一者是為晶粒。
範例3包括範例1-2中之任一者的電子總成，其中，該第二電子裝置被銲接到該第一電子裝置。
範例4包括範例1-3中之任一者的電子總成，其中，在該第一電子裝置中的空穴部份地延伸通過該第一電子裝置。
範例5包括範例1-4中之任一者的電子總成，其中，該第一電子裝置包括一中介層在該第一電子裝置的前側上，且其中，在該第一電子裝置中的空穴延伸通過該第一電子裝置到該中介層。
範例6包括範例5的電子總成，其中，該第二電子裝置被安裝到該中介層。
範例7包括範例1-6中之任一者的電子總成，其中，該第一電子裝置包括電氣連接到該第二電子裝置的貫穿矽通孔。
範例8包括一個包括一基體和一被安裝於該基體上之第一電子裝置的電子封裝體。該第一電子裝置包括一延伸至該第一電子裝置之背側內的空穴。一第二電子裝置被安裝到該第一電子裝置位在該第一電子裝置中的空穴之內。
範例9包括範例8的電子封裝體，其中，該第一電子裝置包括把該第二電子裝置電氣連接到該基體的貫穿矽通孔。
範例10包括範例8-9中之任一者的電子封裝體而且更包括一被安裝到該第一電子裝置與該第二電子裝置中之至少一者的第三電子裝置。
範例11包括範例10的電子封裝體，其中，該第三電子裝置被安裝到該第一電子裝置與該第二電子裝置。
範例12包括範例10-11中之任一者的電子封裝體，其中，該第三電子裝置被銲接到該第一電子裝置與該第二電子裝置中之至少一者。
範例13包括範例10-12中之任一者的電子封裝體，其中，該第一電子裝置、該第三電子裝置與該第三電子裝置中之至少一者是為晶粒。
範例14包括範例8-13中之任一者的電子封裝體，其中，該第二電子裝置被銲接到該第一電子裝置。
範例15包括範例8-14中之任一者的電子封裝體，其中，在該第一電子裝置中的空穴部份地延伸通過該第一電子裝置。
範例16包括範例8-14中之任一者的電子封裝體，其中，該第一電子裝置包括一中介層在該第一電子裝置的前側上，且其中，在該第一電子裝置中的空穴延伸通過該第一電子裝置到該中介層。
範例17包括範例8-16中之任一者的電子封裝體，其中，該第一電子裝置包括把該第一電子裝置電氣連接到該第二電子裝置的貫穿矽通孔。
範例18包括一個包括一基體與一被安裝於該基體上之第一電子裝置的電子封裝體。該第一電子裝置被銲接到該基體並且包括一延伸至該第一電子裝置之背側內的空穴。一第二電子裝置被銲接到該第一電子裝置位在該第一電子裝置中的空穴之內而一第三電子裝置被銲接到該第一電子裝置與該第二電子裝置中之至少一者。
範例19包括範例18的電子封裝體，其中，該第一電子裝置、該第二電子裝置與該第三電子裝置中之至少一者是為晶粒。
範例20包括範例18-19的電子封裝體，其中，在該第一電子裝置中的空穴部份地延伸通過該第一電子裝置。
本電子總成與電子封裝體的這些及其他範例與特徵將會部份地在該詳細說明中作陳述。
這概觀是傾向於提供本主題的非限制性範例。其不是傾向於提供排除或詳盡的說明。詳細說明被包括來提供關於在此中所述之電子總成30及/或電子封裝體60的進 一步資訊。
以上的詳細說明包括對形成該詳細說明之一部份的該等附圖的參照。該等圖式通過描繪的方式顯示能夠實施本發明施的特定實施例。這些實施例於此中也被稱為"範例"。如此的範例能夠包括除了被顯示或描述的那些之外的元件。然而，發明人也考量僅被顯示或描述之那些被提供的範例。再者，發明人也考量使用被顯示或描述之那些元件(或一個或多個其之特徵)之任何組合或排列的範例，無論是相對於一個特定範例(或一個或多個其之特徵)，或相對於在此中所述的其他範例(或一個或多個其之特徵)。
在這文件中，該等詞彙"一(a)"或"一(an)"是被使用，如同在專利文件中很普遍一樣，包括一個或一個以上，與任何其他例子或"至少一個"或"一個或以上"的用法無關。在這文件中，該詞彙"或"是被使用來指出非排他性或，以致於"A或B"包括"A但非B"、"B但非A"、及"A與B"，除非另有說明。在這文件中，該等詞彙"包括"及"在其中"是被使用作為對應詞彙"包含"及"其中"的純英語等效性(plain-English equivalents)。而且，在後面的申請專利範圍中，該等詞彙"包括"和"包含"是開放式的，即，包括除了在申請專利範圍中之如此之詞彙後所列出之那些之外之元件的一系統、裝置、物件、合成物、方程式、或者製程是依然被視為落在該申請專利範圍的範圍之內。再者，在後面的申請專利範圍中，該等詞彙”第一”、”第二”、和”第三”等等是僅被使用作為標籤，而不是傾向於把數值要求加在 它們的對象上。
以上說明是傾向為例示性，而非限制性。例如，上述範例(或者其之一或多個特徵)可以被互相組合使用。其他的實施例能夠由諸如熟知此項技術之人仕在檢閱以上說明時被使用。
說明書摘要是被提供俾遵守37 C.F.R.§1.72(b)，以允許閱讀者快速地弄清楚技術揭露的本質。它是在它將不被用於解釋及限制申請專利範圍的範圍或含義的理解之下被提交。
而且，在以上詳細說明中，各種特徵是可以被組合在一起以簡化該揭示。這不應該被解釋為意圖使該一個未請求的揭示特徵是任何權利要求必不可少的。相反的，發明標的可以少於特定揭示的實施例的所有特徵。因此，下面的權利要求由此被結合到詳細說明中，每個權利要求本身代表一個單獨的實施例，並且可以預期的是這樣的實施例可以彼此以各種組合或置換進行組合。本發明的範圍應參考後附的權利要求，連同如此之權利要求所享有之等效物的全部範圍來判定。

Claims (7)

  1. 一種電子總成，其包含：一第一積體電路晶粒，其包括延伸進入該第一積體電路晶粒之一背側的一多側式空穴，其中該第一積體電路晶粒包括連接該多側式空穴之每一側與該多側式空穴之一平面的底表面的部分，其中該部分與該多側式空穴之每一側及該平面的底表面係相同材料，且其中該平面的底表面從該多側式空穴之每一側延伸至該多側式空穴之每一其它側；一第二積體電路晶粒，其安裝至該第一積體電路晶粒之位於在該第一積體電路晶粒中的該多側式空穴內，其中該第二積體電路晶粒包括一前側及一背側，該前側接合在該第一積體電路晶粒中之該多側式空穴的該平面的底表面；以及一散熱器，其接合該第一積體電路晶粒之該背側及該第二積體電路晶粒之該背側，其中該散熱器包括一側與該第一積體電路晶粒的一側平行，且該該散熱器之該側在該第一積體電路晶粒的該背側下方延伸，以覆蓋該第一積體電路晶粒之側表面，其中在該第一積體電路晶粒中之該多側式空穴延伸以部份地通過該第一積體電路晶粒。
  2. 如請求項1之電子總成，其中該第二積體電路晶粒係被銲接至該第一積體電路晶粒。
  3. 如請求項1之電子總成，其中該第一積體電路晶粒包括被電氣地連接至該第二積體電路晶粒的貫穿矽通孔。
  4. 一種電子封裝體，其包含：。一基體；一第一積體電路晶粒，其包括一前側及一背側，該第一積體電路晶粒之該前側被安裝於該基體上，該第一積體電路晶粒包括延伸進入該第一積體電路晶粒之一背側的一多側式空穴，其中該第一積體電路晶粒包括連接該多側式空穴之每一側與該多側式空穴之一平面的底表面之一部份，其中該部分與該多側式空穴之每一側及該平面的底表面係相同材料，且其中該平面的底表面從該多側式空穴之每一側延伸至該多側式空穴之每一其它側；一第二積體電路晶粒，其安裝至該第一積體電路晶粒之位於在該第一積體電路晶粒中的該多側式空穴內，其中該第二積體電路晶粒包括一前側及一背側，該前側接合在該第一積體電路晶粒中之該多側式空穴的該平面的底表面；以及一散熱器，其包括與該第一積體電路晶粒的側面平行的側表面，且該等側表面在該第一積體電路晶粒的該背側下方延伸，其中該散熱器接合該第一積體電路晶粒之該背側、該第二積體電路晶粒之該背側及該基體，使得該散熱器及該基體包圍該等第一及第二積體電路晶粒，其中在該第一積體電路晶粒中之該多側式空穴延伸以部份地通過該第一積體電路晶粒。
  5. 如請求項4之電子封裝體，其中該第一積體電路晶粒包括將該第二積體電路晶粒電氣地連接至該基體的貫穿矽通孔。
  6. 如請求項4之電子封裝體，其中該第二積體電路晶粒係被銲接至該第一積體電路晶粒。
  7. 一種電子封裝體，其包含：一基體；一第一積體電路晶粒，其包括一前側及一背側，該第一積體電路晶粒之該前側被銲接至該基體，該第一積體電路晶粒包括延伸進入該第一積體電路晶粒之一背側的一多側式空穴，其中該第一積體電路晶粒包括連接該多側式空穴之每一側與該多側式空穴之平面的底表面之部份，其中該部分與該多側式空穴之每一側及該平面的底表面係相同材料，且其中該平面的底表面從該多側式空穴之每一側延伸至該多側式空穴之每一其它側；一第二積體電路晶粒，其被銲接至該第一積體電路晶粒之位於在該第一積體電路晶粒中的該多側式空穴內，其中該第二積體電路晶粒包括一前側及一背側，該前側接合在該第一積體電路晶粒中之該多側式空穴的該平面的底表面；以及一散熱器，其接合該第一積體電路晶粒之該背側，其中該散熱器包括一側與該第一積體電路晶粒的一側平行，且該該散熱器之該側在該第一積體電路晶粒的該背側下方延伸，使得該散熱器覆蓋該第一積體電路晶粒之側表面，其中在該第一積體電路晶粒中之該多側式空穴延伸以部份地通過該第一積體電路晶粒。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2659980C2 (ru) 2014-07-02 2018-07-04 Интел Корпорейшн Электронный узел, который включает в себя уложенные друг на друга электронные устройства
US9583426B2 (en) 2014-11-05 2017-02-28 Invensas Corporation Multi-layer substrates suitable for interconnection between circuit modules
US10283492B2 (en) * 2015-06-23 2019-05-07 Invensas Corporation Laminated interposers and packages with embedded trace interconnects

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200913214A (en) * 2007-07-24 2009-03-16 Micron Technology Inc Semiconductor dies with recesses, associated leadframes, and associated systems and methods
US20130181354A1 (en) * 2012-01-12 2013-07-18 Broadcom Corporation Semiconductor Interposer Having a Cavity for Intra-Interposer Die
US20140159247A1 (en) * 2012-12-06 2014-06-12 Texas Instruments Incorporated 3D Semiconductor Interposer for Heterogeneous Integration of Standard Memory and Split-Architecture Processor

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100234719B1 (ko) * 1997-03-14 1999-12-15 김영환 에리어 어레이 패키지 및 그 제조방법
US7098070B2 (en) * 2004-11-16 2006-08-29 International Business Machines Corporation Device and method for fabricating double-sided SOI wafer scale package with through via connections
EP2033282B1 (en) * 2006-06-16 2012-10-31 Russian limited liability company "Connector Optics" Optoelectronic device for high-speed data transfer
KR100840788B1 (ko) * 2006-12-05 2008-06-23 삼성전자주식회사 칩 적층 패키지 및 그 제조 방법
US8264846B2 (en) * 2006-12-14 2012-09-11 Intel Corporation Ceramic package substrate with recessed device
TWI335059B (en) * 2007-07-31 2010-12-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same
KR20100046760A (ko) * 2008-10-28 2010-05-07 삼성전자주식회사 반도체 패키지
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8519537B2 (en) 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
KR101205144B1 (ko) 2010-06-28 2012-11-26 현대제철 주식회사 건축구조용 ｈ형강 및 그 제조방법
KR20120006770A (ko) * 2010-07-13 2012-01-19 주식회사 하이닉스반도체 테스트 모듈 및 이를 이용한 스택 패키지의 제조방법
US8598695B2 (en) * 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
KR101163899B1 (ko) 2010-08-05 2012-07-09 권대식 분수장치
TWI445104B (zh) * 2010-08-25 2014-07-11 Advanced Semiconductor Eng 半導體封裝結構及其製程
US9111912B2 (en) * 2013-05-30 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
RU2659980C2 (ru) 2014-07-02 2018-07-04 Интел Корпорейшн Электронный узел, который включает в себя уложенные друг на друга электронные устройства

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200913214A (en) * 2007-07-24 2009-03-16 Micron Technology Inc Semiconductor dies with recesses, associated leadframes, and associated systems and methods
US20130181354A1 (en) * 2012-01-12 2013-07-18 Broadcom Corporation Semiconductor Interposer Having a Cavity for Intra-Interposer Die
US20140159247A1 (en) * 2012-12-06 2014-06-12 Texas Instruments Incorporated 3D Semiconductor Interposer for Heterogeneous Integration of Standard Memory and Split-Architecture Processor

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