CN103855129A - 半导体装置及用于制作半导体装置的方法 - Google Patents

半导体装置及用于制作半导体装置的方法 Download PDF

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CN103855129A
CN103855129A CN201310656157.5A CN201310656157A CN103855129A CN 103855129 A CN103855129 A CN 103855129A CN 201310656157 A CN201310656157 A CN 201310656157A CN 103855129 A CN103855129 A CN 103855129A
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chip
intermediary layer
tsv
group
terminal
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CN103855129B (zh
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凯文·莱恩
库尔特·P·瓦赫特勒
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本发明涉及一种半导体装置及用于制作半导体装置的方法。标准存储器芯片(150)借助于堆叠到大硅中介层(110)上的小硅中介层(120)而与分裂架构的两个处理器芯片(130、140)垂直组装；两个中介层均包含穿硅通孔TSV，而所述芯片不具有TSV。小中介层(120)的所述TSV连接到所述存储器芯片(150)及所述底部中介层(110)。相对于中介层(120)对称定位且通过短信号迹线连接到中介层(120)的芯片(130、140)附接到中介层(110)的所述TSV，所述中介层(110)又借助供应连接附接到衬底(160)。

Description

半导体装置及用于制作半导体装置的方法
技术领域
本发明一股来说涉及半导体装置及工艺的领域，且更明确地说，涉及用于以分裂架构来垂直堆叠芯片的两个半导体中介层的使用。
背景技术
由于集成电路的发明，因此电路发展的过程是沿着将越来越多的电子功能组合到单个芯片上的电路布局中的方向。众所周知的实例是单个芯片上的逻辑及存储器功能的组合。所述功能由例如电阻器、电容器、二极管及晶体管的电组件建构，所述电组件又通过芯片上的布局而实现。通过比较现代芯片的布局将明了：针对一些布局的组件的制作需要比针对其它布局的组件的制作高的数目个工艺步骤。
芯片上的越来越多的功能的持续趋势加剧了制作步骤的数目的差异，从而导致较高电路复杂性及较大芯片大小、与组件的小型化的持续市场压力组合、导致缩小的特征大小。由于市场进一步强烈地鼓励具有减小的成本及增加的可靠性的产品，因此半导体工业在过去几年中致力于通过使用分离线特性(例如技术节点或者工艺步骤或光掩模步骤的数目)而将具有复杂电路的单个大芯片分成具有紧密相关特征的电路的多个芯片。作为实例，芯片可依照技术节点28nm对20nm或用于单芯片系统的建筑分裂而分离成逻辑(举例来说，无线局域网络芯片)及存储器(举例来说，快闪存储器芯片)。由于快闪存储器需要几个额外光掩模，因此将成本增加局限于仅存储器部分是较经济的。
在决定将过度复杂的芯片分成若干个较经济的芯片之后，不得不发展用于将芯片组装成单个封装的策略。举例来说，继续单芯片系统的建筑分裂的以上实例，所述装置可是经封装芯片堆叠，其中无线局域网络芯片放置为所述堆叠的下部芯片，且快闪存储器芯片作为上部芯片；所述下部芯片借助到外部部分的连接而附接到封装衬底。电线接合将上部芯片互连到下部芯片且将下部芯片互连到衬底；不得不考虑由所述电线造成的不可避免的IR下降。如果产品将试图通过形成穿过底部芯片的金属填充的通孔(所谓的TSV，穿硅通孔)而避免使用接合电线，那么将仍存在关于以下各项的问题：到上部芯片的供应连接，以及连接的充分数目及从上部芯片到衬底的充分热耗散路径。另外，穿过集成电路芯片的TSV添加显著成本且不得不克服关于硅与TSV中的金属之间的不同热膨胀系数(CTE)的问题。
最近已提出通过按单元构建堆叠装置来避免集成电路芯片中的TSV的建议，其中每一芯片倒装连接于具有TSV的个别硅中介层上。为集成积木式部件，中介层具有比芯片大的区，使得其所述芯片区上方形成突出部分；然后，金属柱可提供中介层之间及从中介层到衬底的互连。
发明内容
申请人在市场分析中认识到：只要具有与基于分裂芯片架构的单芯片系统(SOC)有联系的工业标准高带宽存储器芯片的半导体装置(在市场需要时)节省有效面积且是划算的，所述装置便具有众多产品应用。通过研究分裂芯片架构的实例，可依照20nm技术的规范制作较高性能的第一子芯片，而可依照28nm技术的规范制作较低性能的第二子芯片。借助穿硅通孔(TSV)技术来组装子芯片与存储器芯片的方法将需要在SOC的子芯片中形成TSV，使得子芯片可堆叠于在顶部上具有存储器芯片的衬底上。申请人发现以任何次序的垂直组装均可造成子芯片的供应问题(IR下降限制)及热耗散问题。
申请人进一步发现采用标准硅中介层来并排组装分裂SOC架构的芯片及将中介层附接到衬底的另一方法将仅将宽带宽连接提供到两个SOC芯片中的一者，而不将宽I/O连接提供到另一芯片。用于将宽I/O存储器连接到第二芯片的标准中介层的信号路径将变得过长。此外，所述组装将是非对称的且产生存储器芯片到一侧的突出部分，从而造成总体装置的大小增加，导致不平衡应力及可靠性问题。
申请人在其发现利用彼此上下堆叠的具有穿硅通孔(TSV)的两个硅中介层的3D中介层概念时，解决了将标准存储器垂直堆叠到分裂架构的两个芯片的问题。顶部中介层连接到存储器芯片，而底部中介层包含到分裂架构的两个芯片的短且优选地对称的信号路径。两个芯片均附接到所述底部中介层且不需要TSV；所述底部中介层又附接到衬底。
本发明的示范性实施例具有第一硅中介层，所述第一硅中介层跨越所述中介层区具有经排列的三组TSV。第一组允许分裂SOC架构的第一芯片的附接，且第二组允许SOC架构的第二芯片的附接。大约定位于所述第一组与所述第二组之间的中间的第三组在所述第三组的区域中允许到垂直定位于所述第一中介层上的第二中介层的TSV的连接。标准存储器芯片垂直附接到所述第二中介层的所述TSV且通过从所述第一中介层的所述第三TSV组到所述第一TSV组及所述第二TSV组的水平迹线而连接到所述分裂SOC架构的所述两个芯片。所述第二中介层与所述第一中介层相比具有相对小的大小。
技术优点是：申请人的解决方案提供堆叠芯片装置的大约对称构造，因此使所需板有效面积最小化且避免所述装置内的不平衡热机械应力，从而增强装置可靠性。
申请人的解决方案的另一技术优点是：分裂SOC架构的两个芯片不需要TSV，使得所需TSV保持限制于两个硅中介层，从而保持尽可能低的成本，所述两个芯片需要前沿技术处所涉及的前端工艺流程且因此是有价值的。
作为另一技术优点，使用TSV提供与电线接合相比显著较低的电感及电阻，且还提供关于较短及较小的未来TSV的良好的电感比例调整。
附图说明
图1图解说明本发明的示范性实施例的横截面，其展示用于将标准存储器芯片垂直堆叠到分裂SOC架构的芯片的具有TSV的两个硅中介层。
图2是示范性第一中介层的俯视图，其指示用于具有分裂架构的两个芯片及第二中介层的组装位点。
图3展示作为金属填充的导通孔的穿硅通孔(TSV)的剖面图，所述穿硅通孔连同互连表面迹线的部分一起从硅晶片的一个表面延伸到相对表面。
具体实施方式
图1图解说明作为本发明的实施例的通常标示为100的示范性半导体装置。装置100包含第一硅中介层110、第二硅中介层120、第一半导体芯片130、第二半导体芯片140及第三半导体芯片150。装置100进一步包含衬底160，且还可包含囊封中介层110及120、第一芯片130及第二芯片140以及第三芯片150的至少部分的封装化合物170。第三芯片150的未囊封表面150b可充当散热器或散热片的附接位点，从而促进堆叠装置100的有效冷却。
如图1展示，第一硅中介层110具有厚度110d、第一表面110a及相对第二表面110b；厚度110d优选地为50μm，但其它中介层可较厚或较薄。多个穿硅通孔(TSV)从第一表面110a穿过第一中介层110延伸到第二表面110b。多个TSV排列成第一组111、第二组112及第三组113。在示范性布置中，针对具有分裂架构的处理器及标准存储器的情形而在图2显示这些组。然而，这些实例不应理解为限制性意义，这是因为大数目个半导体装置系列提供众多类似实例。
图2指示邻近TSV彼此平行。在到半导体材料的界面处，每一TSV的侧壁是笔直的，但未必彼此平行；优选地，TSV具有圆柱形形状，如图3中的TSV的放大形式中所展示。在一些实施例中，侧壁可具有截锥形的形状。在其它实施例中，孔的横截面可是矩形的、六边形的或呈与半导体材料的结晶定向相配的任何其它轮廓。经蚀刻TSV的直径301优选地在大约10μm到40μm的范围内进行选择；优选选择为25μm。
实践若干种方法来制作如图3中所图解说明的TSV：导通孔可是敞开的且作为工艺流程中的第一步骤而被填充，或在已制作导电迹线及某一电路之后被填充，或作为制作导电迹线及电路之后的最后步骤而被填充。在优选方法中，蚀刻用于TSV的孔，而半导体材料仍呈晶片形式且具有介于70μm到150μm的范围内的深度302。电介质化合物(例如氮化硅或二氧化硅)在蚀刻步骤之后沉积于TSV侧壁上以便在半导体材料与TSV内侧的导电化合物之间形成薄(＜1μm)绝缘衬里303。
此后，将金属种子层沉积(厚度＜1μm)于绝缘层(图3中未展示)上。种子金属或金属化合物的选择取决于用于填充TSV的金属的选择；优选种子金属为氮化钽。然后，用金属304填充经蚀刻孔；优选填充物金属为铜。可在晶片薄化(研磨)工艺之前或在薄化步骤之后执行填充物金属的沉积。在用金属填充(在填充之后的一些装置中)导通孔之前，形成经图案化金属层116的网状物，所述网状物提供中介层表面110b上的互连。可通过将镍层116b(接着将钯或金层)沉积于部分116a上而将金属116的经暴露部分116a制成为可焊接的。
通过研磨或蚀刻或者两者而薄化晶片的工艺步骤继续直到暴露导通孔的底部且可接达所沉积金属为止。可继续所述薄化步骤达额外短时间周期以暴露填充金属304的端部部分304a；随后，可用可焊接金属层305(例如镍、钯、金或这些层的组合)覆盖端部部分304a。剩余半导体厚度302对于一些装置优选地为大约50μm且对于其它装置优选地为大约100μm。
在薄化步骤之后，倒置用于制作中介层的硅晶片，使得原始表面110b(称为第二表面)变为底部，且可将绝缘层310沉积于第一表面110a上。举例来说，可使用聚酰亚胺化合物，接着为经图案化金属连接115，所述经图案化金属连接(举例来说)可由铜或共晶金锗合金(Ge的重量为12.5％，共晶温度为361℃)制成；导电连接115a提供到TSV的电接触。为在组装过程中形成连接，可焊接层305及116b连同小量的低熔化温度焊料一起形成高熔点金属间化合物，使得所述连接耐受温度偏差且将不会因焊料回流而断开。
图2图解说明具有矩形形状的示范性第一中介层110的俯视图；其它第一中介层可为具有10mm乘10mm或12mm乘12mm或其它尺寸的示范性侧长度的正方形形状。如图2中所图解说明，第一TSV组111位于第一中介层区域211中，所述第一TSV组在图2中靠近于所述中介层的外围110c。图2中未个别地展示TSV，但第一组111的TSV与第一半导体芯片130的端子匹配；取决于装置类型，所述TSV的数目可为几百到一千多个。第一组111包含TSV的子组111a(也未个别地展示，可为一千多个)，所述子组与第一芯片130的存储器I/O的端子匹配。而对于许多装置类型，子组111a位于组111的中心内，在图2的示范性实施例中，子组111不位于组111的中心内。在示范性实施例中，第一芯片130可为分裂TOC架构的高性能芯片、可具有50μm的厚度130d且可(举例来说)通过相对先进的半导体技术(例如20nm技术)而制作。在示范性实施例中，芯片130可具有4mm乘12mm的大小。
如图1展示，芯片130的端子通过焊料凸块131附接到第一中介层表面110a上的组111的匹配TSV。或者，可代替焊料凸块使用铜柱(举例来说，具有30μm直径)。如通常所表达，芯片130“倒装”于中介层110上；因此，芯片130垂直堆叠于第一中介层110的第一表面110a上。在通过焊料凸块的附接之后，第一芯片130的厚度130d连同焊料凸块的高度132在本文中称为第一高度。
技术优点是：第一芯片130可保持不具有TSV，即，避免否则显著成本增加的事实。
如图2中所图解说明，第二TSV组112位于第二中介层区域212中，所述第二TSV组相对于第一TSV组111在图2中靠近于中介层外围110e。图2中未个别地展示TSV，但第二组112的TSV与第二半导体芯片140的端子匹配；取决于装置类型，所述TSV的数目可为几百到一千多个。第二组112包含TSV的子组112a(也未个别地展示，可为一千多个)，所述子组与第二芯片140的存储器I/O的端子匹配。如图2的示范性实施例图解说明，子组112a不必位于组112的中心内，但对于许多装置类型，子组112a确实位于中心处。在示范性实施例中，芯片140可为分裂TOC架构的较低性能芯片、可具有50μm的厚度140d且可(举例来说)通过相对成熟的半导体技术(例如28nm技术)而制作。在示范性实施例中，芯片140可具有6mm乘12mm的大小。
如图1展示，芯片140的端子141通过焊料凸块附接到第一中介层表面110a上的组112的匹配TSV。或者，可代替焊料凸块使用铜柱。如通常所表达，芯片140“倒装”于中介层110上；因此，芯片140垂直堆叠于第一中介层110的第一表面110a上。在通过焊料凸块的附接之后，第二芯片140的厚度140d连同焊料凸块的高度142在本文中称为第二高度。
技术优点是：第二芯片140可保持不具有TSV，即，避免否则显著成本增加的事实。此外，应提及，由于硅的高导热性，第一中介层110帮助由芯片(尤其由高性能芯片130)形成的操作热的热耗散。
如图2中所图解说明，第三TSV组113位于第一中介层区域211与第二中介层区域212之间，优选地大约在中介层的中间。更优选地，第三组113在第一组111与第二组112之间是对称的。图2中未个别地展示TSV(可为一千多个)，但第三组的TSV与第三半导体芯片150的端子匹配。在示范性实施例中，芯片150可为具有优选地位于芯片的中心区域中的端子的标准存储器芯片。第三组的TSV提供到存储器芯片150的直接电源及接地连接。
图1指示第三组113的TSV具有到第一组111及第二组112的TSV的导电迹线114(图2中未展示迹线)。迹线114将存储器互连分布到第一芯片130的端子及第二芯片140的端子。在优选实施例中，迹线114采取到第一芯片130及第二芯片140的相应TSV的最短路线，使得IR损失及其它寄生损失最小化。与中介层110集成在一起的额外迹线提供芯片130与140之间的互连。
在优选实施例(参见图1)中，第二硅中介层120具有大约2mm乘12mm的面积及50μm的高度；此大小与第一中介层110相比较小，第一中介层110可具有10mm乘10mm或12mm乘12mm的示范性面积。第二中介层120具有第三表面120a及相对第四表面120b。多个穿硅通孔(TSV)从第三表面120a穿过第二中介层120延伸到第四表面120b。多个TSV与第三半导体芯片150的端子匹配。TSV穿过第二中介层120的表面120a及表面120b的端部优选地是可焊接的。第二中介层120的匹配TSV通过焊料凸块121附接到第一中介层表面110a上的第三组113的相应TSV。或者，可代替焊料凸块使用铜柱。因此，中介层120垂直堆叠于中介层110的第一表面110a上，从而赋予第一中介层120三维(3D)中介层的特性。
如图1指示，第二中介层120连同用于附接到第一中介层110的焊料凸块121的高度122至少与第一高度132及第二高度142一样大。
图1的具有第二硅中介层120的示范性实施例的技术优点是：通过使用具有JEDEC标准界面的标准存储器芯片150，可避免采用具有到两个芯片130及140的两个界面的定制存储器；所述方法将导致不可解决的对准准确性问题。
使用连接到第一(大)中介层的第二(小)中介层的另一技术优点是：第一中介层提供从第二中介层到平行的(分裂架构的)两个芯片的连接、芯片之间的进一步短距离连接及到两个芯片的进一步良好供应连接，从而减轻IR问题。所述堆叠架构可是对称的，从而避免不平衡应力。
额外技术优点是：由硅制成的中介层提供改进的热耗散以及与所述芯片相同的膨胀系数，且因此避免热机械应力。
第三芯片150(其优选地为标准存储器芯片)的端子优选地通过焊料凸块151焊接到第二中介层120的TSV。焊料凸块连同高度122(其至少与高度132及高度142一样大)的额外高度确保芯片150不触碰芯片130及芯片140。因此，第三芯片150垂直堆叠于第二中介层120上，但与芯片130及140分离。此外，第三芯片150可保持不具有TSV，从而避免否则显著成本增加。
第一、第二及第三组的TSV的端部暴露于第一中介层110的第二表面110b上。这些TSV端部优选地是可焊接的且可通过经图案化金属层116互连。或者，第一、第二及第三组的TSV可以表面110b上的可焊接金属垫结束。
图1指示装置100进一步包含由绝缘材料制成且与导电垂直及水平迹线集成在一起的衬底160。对于图1的示范性装置100，衬底可为具有14mm乘14mm或16mm乘16mm的侧长度的正方形形状。衬底160优选地在其面向第一中介层的第二表面110b的表面160a上具有可焊接接触垫。多个这些接触垫与TSV穿过中介层110的端部及第一中介层的第二表面110b上的金属垫匹配。如图1中所描绘，焊料凸块118连接中介层TSV端部及表面110b上的金属垫与衬底接触垫。或者，可使用铜柱(举例来说，具有30μm直径)用于互连。因此，第一中介层110垂直堆叠于衬底160上。
衬底160在其与第一中介层110相对的表面160b上具有适于互连到包含电力供应器及电接地的外部部分的接触垫161。焊料凸块的数目可较高，使得可有效地避免IR下降问题。作为优选实例，图1描绘作为互连构件的焊料球170。或者，压力触点可用于连接到垫161。
在图1中所图解说明的示范性实施例中，焊料凸块用于互连芯片及中介层；然而，如所提及，替代互连方法采用铜柱。当使用焊料凸块时，选定用于特定工艺步骤的焊料化合物的回流温度优选地应低于经采用用于先前步骤的焊料化合物的回流温度，使得在先前组装步骤中制成的互连将不再熔化。因此，在优选工艺流程中，凸块151的回流温度＜凸块131、141及121的回流温度＜凸块118的回流温度。当采用焊料凸块170用于将装置100连接到外部部分时，优选地，凸块170的回流温度＜凸块151的回流温度。
当使用铜柱时，附接到柱尖端及打算用于互连的焊料量优选地保持如此小使得所述焊料化合物在组装过程期间完全被消耗以形成金属间化合物。由于金属间化合物的再熔化温度较高，因此通常在后续附接步骤期间不存在断开先前所形成的连接的风险。
虽然已参考说明性实施例描述了本发明，但此说明并非打算解释为限制性意义。所属领域的技术人员参考所述说明将明了说明性实施例的各种修改及组合以及本发明的其它实施例。作为实例，存储器芯片不必为标准存储器芯片，而可为任何存储器芯片。作为另一实例，中介层可由具有接近于电路芯片的热膨胀系数(CTE)的CTE的任何材料制成。
作为又一实例，包含大大小及小大小的中介层的三维半导体中介层的概念可适用于任何三个电路芯片的组装，其中小大小的中介层约附接在大大小的中介层的中间，所述大大小的中介层具有经定位与小大小的中介层约对称的芯片中的两者。
因此，所附权利要求书打算囊括任何此类修改或实施例。

Claims (14)

1.一种半导体装置，其包括：
第一硅中介层，其具有第一表面及相对第二表面以及第一TSV，所述第一TSV从所述第一表面穿过所述第一中介层延伸到所述第二表面，所述第一TSV排列成第一组、第二组及第三组；
所述第一组位于第一中介层区域中且与焊接到所述第一组的第一芯片的端子匹配，其中所述第一芯片垂直堆叠于所述第一中介层的所述第一表面上，所述第一芯片连同焊料具有第一高度；
所述第二组位于第二中介层区域中且与焊接到所述第二组的第二芯片的端子匹配，其中所述第二芯片垂直堆叠于所述第一中介层的所述第一表面上，所述第二芯片连同所述焊料具有第二高度；且
所述第三组位于所述第一区域与所述第二区域之间且与第二硅中介层的端子匹配，所述第三组的所述TSV通过导电迹线连接到所述第一组及所述第二组的TSV；
第二硅中介层，其具有第三表面及相对第四表面以及第二TSV，所述第二TSV从所述第三表面穿过所述第二中介层延伸到所述第四表面，所述第二TSV与第三半导体芯片的端子匹配；
所述第二中介层焊接到所述第三TSV组，其中所述第二中介层垂直堆叠于所述第一中介层上，所述第二中介层连同所述焊料的高度至少与所述第一高度及所述第二高度一样大；且
所述第三芯片焊接到所述第二中介层，其中所述第三芯片垂直堆叠于所述第二中介层上。
2.根据权利要求1所述的装置，其中所述第一芯片及所述第二芯片为具有分裂架构的单芯片系统的部分。
3.根据权利要求2所述的装置，其中所述第一芯片包含所述单芯片系统的较高性能部分且所述第二芯片包含较低性能部分。
4.根据权利要求3所述的装置，其中所述第三芯片为标准存储器芯片。
5.根据权利要求1所述的装置，其中所述第一芯片、所述第二芯片及所述第三芯片不具有TSV。
6.根据权利要求1所述的装置，其中所述第三TSV组的位置在所述第一区域与所述第二区域之间是对称的。
7.根据权利要求1所述的装置，其中所述第三组TSV的所述导电迹线位于所述第一中介层的所述第一表面上。
8.根据权利要求1所述的装置，其在所述第一中介层的所述第二表面上进一步包含用于所述第一组、所述第二组及所述第三组的所述TSV的可焊接金属垫。
9.根据权利要求1所述的装置，其进一步包含衬底，所述衬底在其面向所述第一中介层的表面上具有与所述第一中介层的所述第二表面上的所述垫匹配的可焊接接触垫。
10.根据权利要求9所述的装置，其进一步包含将所述第一中介层连接到所述衬底接触垫的焊料凸块，其中所述第一中介层垂直堆叠于所述衬底上。
11.根据权利要求9所述的装置，其中所述衬底在其与所述第一中介层相对的表面上具有用于互连到包含电源及接地端子的外部部分的接触垫。
12.根据权利要求1所述的装置，其中所述第一TSV具有在所述第一表面上的第一可焊接端部及在所述第二表面上的第二可焊接端部，且所述第二TSV具有在所述第三表面上的第三可焊接端部及在所述第四表面上的第四可焊接端部。
13.根据权利要求1所述的装置，其进一步包含囊封所述第一芯片、所述第二芯片及所述第三芯片以及所述第一中介层及所述第二中介层的聚合封装化合物。
14.一种用于制作半导体装置的方法，其包括以下步骤：
提供具有第一端子的第一芯片、具有第二端子的第二芯片及具有第三端子的第三芯片；
提供具有第一TSV的第一硅中介层及具有第二TSV的第二硅中介层，所述第一TSV排列成第一组、第二组及第三组；所述第一组位于第一中介层区域中且与所述第一端子匹配；所述第二组位于第二中介层区域中且与所述第二端子匹配；且所述第三组位于所述第一区域与所述第二区域之间的第三中介层区域中且与所述第二中介层的所述TSV及所述第三端子匹配；
将所述第一芯片与所述第一组TSV对准、所述第二芯片与所述第二组TSV对准及所述第二中介层与所述第三组TSV对准；
使用第一熔化温度的焊料。
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