TW201342523A - 用於只包含已驗證的電路板的三維電子模組之集體製造的方法 - Google Patents

用於只包含已驗證的電路板的三維電子模組之集體製造的方法 Download PDF

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TW201342523A
TW201342523A TW101149589A TW101149589A TW201342523A TW 201342523 A TW201342523 A TW 201342523A TW 101149589 A TW101149589 A TW 101149589A TW 101149589 A TW101149589 A TW 101149589A TW 201342523 A TW201342523 A TW 201342523A
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stack
kgrp
printed circuit
kgrw
cutting
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TW101149589A
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TWI591758B (zh
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Christian Val
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3D Plus
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Abstract

本發明係關於一種3D電子模組之集體製造的方法，其包含：- 製造重建晶圓之堆疊的步驟，包含驗證的主動組件，此堆疊包括再分配層，- 製造已驗證被動印刷電路的平板，其包含下列子步驟：○製造印刷電路之平板，○每個印刷電路之電性測試，○裝配已驗證的印刷電路至附著基板，○鑄模安裝的電路於電性絕緣樹脂，所謂塗佈樹脂及樹脂之聚合，○移除附著基板，藉此獲得只包含已驗證的印刷電路(200)的平板，- 將平板與堆疊(重建晶圓的)接合的步驟，- 為了獲得3D電子模組之目的切割「平板之堆疊」組合件之步驟。

Description

用於只包含已驗證的電路板的三維電子模組之集體製造的方法
本發明領域係為3D電子模組之製造的領域。
3D電子模組，其範例如圖1所示，包含藉由特別使用堆疊面於三維中互連的電子薄片(slice)50之堆疊100以生產介於薄片之間的連接。一個薄片50通常包含一或多個具有電子連接元件2之主動及/或被動組件11，此組件塗佈上電性絕緣樹脂6。組件的連接元件2連接至由電性絕緣基板4支撐的連接針腳2’。由絕緣基板4支撐的一或多個電性導電走線3將這些組件一起連接至或將他們連接至用於一起電性連接薄片的元件。3D電子模組在薄片的其中一者中包含至少一個主動組件。
這些薄片50已由來自重建的晶圓(亦稱KGRW，其代表已知良好重建晶圓(Known Good Reconstructed Wafers))之集體製造所獲得，他們本身於下列步驟期間完成：
A)定位且固定至以他們連接針腳2裝備之基板裸露(=未封裝)主動及/或被動矽組件11，在測試之後，這些組件已較佳的被驗證；連接針腳與基板接觸。此基板一般為黏皮(sticky skin)類型之附著的薄片。
B)將多晶矽層，像是環氧樹脂(epoxy resin)6置放於組件及基板組合上。
C)移除基板(黏皮)，D)再分配針腳以連接一個及同樣的線路圖形(pattern)之所有組件11及/或為了後續3D互連的目的完成對線路圖形之周邊的連接。為了此目的，置放了在用以設置組件11至其它組件及/或至其它周邊連接而金屬導電走線3所形成處上可蝕刻類型的絕緣材料4的層。絕緣層4選擇性的置放在導電走線3上。在某些複雜連接的情況下，些許的絕緣體+金屬+選擇性的絕緣體(=層級(level))層能夠互相的置放。這已生產具有一個或多個層級之所謂RDL再分配層30。在圖中，每個薄片之RDL層具有單一層級。
這已生產「KGRW」重建晶圓，其因此只包含先前測試及已驗證的薄片。
E)當些許的KGRW晶圓已被製造時，他們接著被堆疊。
F)針腳再分配層30，所謂再分配層的RDL，係形成於堆疊之面的其中之一者，因此形成堆疊的「第一」層。此RDL層一般包含1至4層級(或子層)並且在切割步驟之前形成在晶圓堆疊上，也就是說於集體製造方法期間。在圖中其具有兩層級。
晶圓的堆疊被切割以獲得薄片的堆疊100。
導體33處於薄片之堆疊的側面，也就是說在薄片的邊緣上並且可選擇的在其中一面上，且所謂的側向導體(lateral conductor)係形成以將一個薄片的組件電性連接 至其它薄片。
這類方法的範例在專利FR2 857 157中說明。
然而，對於一個薄片50及/或對於薄片之堆疊100的第一層來說，其通常需要具有大於4個層級的再分配層(RDL；redistribution layer)：6至10個連接層級通常是必要的。但RDL層的良率(yield)隨著在層級的數目上的增加而快速的降低。對於一個薄片來說，其一般自以具有一層之RDL的96%良率降低至用於具有四個層級的RDL之80%；因此不生產具有6個或更多的層級的RDL。
結果是，現有保留對於3D電子模組之集體製造之方法的需要，其同時滿足所有前述依照再分配層及良率之數目的要求(已驗證的數目/製造的數目)。
本發明的原理為：- 一方面，藉由印刷電路或是印刷電路板(Printed Circuit Board)之PCB，提供介於堆疊的3D電子模組之薄片之間的電性連接(使用半導體工業技術獲得堆疊)，其使得具有更多的連接層是可能的，以及- 另一方面，藉使用100%良好的PCB之平板由集體製造獲得3D電子模組，其使得增加全體製造良率是可能的。
本發明的標的係為3D電子模組之集體製造方法，其 包含：- 一個步驟為，製造所謂KGRW之N個重建晶圓(N1)之堆疊，其每個只包含測試之後已驗證的一致(identical)的線路圖形，一個線路圖形包含至少一個主動及/或被動矽組件、包含主動組件之至少一個重建晶圓，此堆疊包括具有最大4個互連層級之再分配層，其特徵在於：- 一個步驟為，製造一致的被動印刷電路之平板，其只包含被動印刷電路(其包含至少6個互連層級)，並且於測試之後驗證，其包含下列子步驟：￮製造一致印刷電路板之平板，￮電性測試每個印刷電路，￮在這些測試後裝配(fit)已驗證的印刷電路至附著基板，￮鑄模安裝的電路於電性絕緣的環氧類型之樹脂，所謂塗佈樹脂及樹脂之聚合，￮移除附著基板，藉此於此步驟後獲得只包含已驗證印刷電路平板，所謂KGRP之平板，- 接合步驟，將KGRP平板與KGRW堆疊接合，其係為了形成「KGRWs-KGRP平板之堆疊」的組合件(assembly)，- 切割步驟，沿著為了獲得3D電子模組之目的之切割線切割「KGRWs-KGRP平板之堆疊」的組合件。
依據本發明之一個特徵，其包含，介於接合步驟與切 割步驟之間，在KRGP平板上，生產具有厚度小於30μm之再分配層之步驟。
切割線較佳的在塗佈樹脂上。
由於「KGRWs-KGRP平板之堆疊」組合件包含在其厚度上至少一個電性絕緣區(electrically insulating zone)，其選擇性的包含介於接合KRGP之步驟以及切割步驟之間的突穿在該電性絕緣區中的開孔之步驟，以及以電性導電材料填充這些開孔之步驟。
能夠製造些許KGRW堆疊及/或些許KGRP平板：在切割步驟之前，藉此反覆將KGRW堆疊與KGRP平板接合之步驟，「KGRWs-KGRPs平板之堆疊」組合件包含些許KGRW堆疊及/或些許KGRP平板。
依據繪示於圖4a及4b中的範例之本發明的3D電子模組至少包含：- N個薄片50(N1)之其中之一個堆疊；此堆疊包含至少一個主動組件所謂主堆疊100並且包括在堆疊之一個面上(或於雙面上)之RDL層30，以及- 印刷電路或PCB 200，其提供介於這些薄片之組件之間的電性連接，此PCB包含至少6個互連層級其本身於該堆疊100上堆疊。
在圖中的厚度並未縮放。
PCB亦可設計為提供介於置放在PCB之一個面上的 兩個主動堆疊之間的連接，在另一個面上的另一者，如能夠在圖4中3D電子模組的範例中所示，其中繪示著每個主動堆疊之僅一個薄片50。更一般的來說，依據本發明之3D電子模組包含一或多個主動堆疊及一或多個PCB。
如於前文中所指出的，3D電子模組(不具有側向導體)於切割堆疊的晶圓之步驟後獲得，堆疊包括第一層、接近30μm厚的RDL層。被考慮的是，KGRW晶圓之堆疊已由使用在半導體工業中所使用的技術生產，其係依據如於前言中所指出的集體製造方法並且包含連續的步驟A、B、C、D、E及F。
目前關注的是印刷電路或PCB之集體製造。
應注意，印刷電路或對於印刷電路板(Printed Circuit Board)之PCB係為電性連接電路，其包含電性導電走線(conductive track)並且可包含被動組件，諸如電容器C、電阻器R及自電感器(self inductor)。PCB一般包含50至500個旁路電容器(bypass capacitor)，其將各別的連接至主動組件(亦所謂晶片)及/或主動堆疊之被動組件。
這些PCB 200正常具有大於6的層級(或層)，其係如在圖2b中所示(具有4個層級以致不使圖過於複雜)，因為他們亦被提供以接地平面以及用於每個所需電壓之孤立電位(isopotential)電源供應，每個平面形成一個層級。
注意PCB組成為： - 由預留用於接地及電源供應平面之內部層201，並且可選擇的包含信號佈線(signal-routing)平面，在其中之重疊(superposition)形成內部層之平板，- 以及通常由提供用於信號之佈線的外部層202組成，其包夾此內部層之平板(當後者產生時)。
內部層之平板之良率係介於90%與95%之間，其係因為僅在測試及驗證後所選的層被壓合於他們之間以形成此平板。但是外部層的良率(其只取決於蝕刻所需要的薄度由在內部層的平板上之一者所建構者)，可變化於75%及90%之間。整體良率(其係為單一良率的產出)因此介於70%與85%之間。PCB 200之平板(在兩部分中)之範例則如圖7所示：4個PCB已視為不良(faulty)，因此良率為83%。
藉此，對於3D模組之集體製造，當這些KGRW堆疊在其中一些為不良的PCB之平板上時，可能失去與使用針對具有良率接近100%之主動堆疊的KGRW相關聯的益處。若主動組件之值遠高於被動元件(PCB)之者時，此是所有更加關注的。這就是為何，依據本發明，將生產僅包含良好的PCB之平板，也就是說僅包含在測試後已被驗證之PCB，以及代表「已知良好重建的PCB(Known Good Reconstructed PCBs)」之選派的KGRP。
先前步驟在於在傳統方式中生產PCB之平板，其包含n個一致的線路圖形(或PCB)，n一般自20變化至1000，其係取決於平板及線路圖形之格式。對於此平板之 製造，使用了用於製造印刷電路之通常技術，也就是說由預先沈積在電性絕緣基板6’(其由環氧樹脂做成)之銅所做成之層的光蝕刻(photoetching)；做成印刷電路從不需要使用矽。此銅層被多層化(laminated)且然後藉壓合至基板之上而置放，其需要對於銅層及對於基板兩者之最小厚度。銅的厚度通常為5 μm至25 μm，其限定走線3’之蝕刻的界定。詳細而言，被化學蝕刻之層的厚度愈大，由於次蝕刻(sub-etching)現象則界定則愈差。在實際上，針對導體3’獲得大於100 μm之間距(pitch)，一般介於100 μm及200 μm之間。注意，間距係為導體寬度與介於兩個導體3’之間的空間的總和。100 μm之間距=50 μm(導體之寬度)+50 μm(介於兩導體之間的空間)。基板6’之厚度於50μm及150 μm之間改變。
為降低形成基板6’之環氧樹脂的膨脹係數(expansion coefficient)，後者包含玻璃纖維；如此一來，此係數由60增加至80 ppm/℃，對於在樹脂中具有玻璃纖維之樹脂僅至15到18 ppm/℃。另一方面，「Z」膨脹係數將保持不變且將介於60及80 ppm/℃之間。
由於平面度(flatness)之需要，用於絕緣之庶罩由平面玻璃做成。
這因此給定了每連接層級最小厚度75 μm(用於薄片之50 μm+用於銅走線之25 μm)。層級在另一者頂端上之者做成以最終形成用於具有10層級之PCB的至少750 μm厚之PCB平板。
僅管如此，隨著用以生產KGRW之光蝕刻技術，在聚合作用(polymerization)之後，由載滿微型珠(microbead-laden)的樹脂(其一般以液體形式存放)做成的基板6具有介於10μm及15 μm之間的厚度以及金屬走線具有1 μm級數的厚度或甚至更小，其使得獲得小於10 μm之間距係為可能的。
每個線路圖形，也就是說每個PCB，接著進行電性測試，並且接著切割平板。
於後續步驟(步驟a，圖3a)期間，在測試後已驗證之PCB 200安裝至例如藉由«取置(pick and place)»類型之方法的附著基板8，其如圖所示每個PCB之互連針腳在附著基板側上。此附著基板可為用於例如像是聚氯乙烯(polyvinyl chloride)薄板(sheet)的附著薄板，一般所謂鼓膜(drumskin)或具有厚度約25 μm之黏皮具其能夠在不以特別的加工(treatment)之下分開，例如藉由剝開。
於步驟b(圖3b)期間，PCB 200接著被塗佈以如對生產KGRW(例如環氧樹脂)者同樣類型的電性絕緣樹脂6，其接著被聚合。
此樹脂6係載滿以矽珠，其用以降低其X、Y及Z膨脹係數(在三個空間方向中)：於生產在如下所述每個3D模組之側面上之導體33的後續步驟期間，其為等向性(isotropic)，同時呈現在PCB之基板6’中的玻璃纖維使得僅在X及Y方向上的基板之膨脹係數是可能的，且 就漏電流而論亦具有缺點。在此情形中，在這些切割線處，為了藉由建構重建如KGRW同樣的結構至其將被堆疊之處上，因而防止這些漏電流，塗佈PCB亦具有在黏皮上固定每個PCB的位置之通常功能、在未來切割線處每層之玻璃纖維之絕緣功能。
一旦PCB已被塗佈，黏皮8則被移除。
平板因此已被生產來僅包含已驗證的PCB，所謂KGRP之平板，也就是說其良率為100%之平板。
在一個層級處之RDL 30生產在PCB平板之外部面上(步驟c，圖3c)以完成對每個PCB 200之周邊的連接。這使得藉由此時使用用以製造晶圓之技術來生產高精確層係為可能的；在具有小間距之暫時的平板導電走線之表面上生產因此是可能的，也就是說小於100 μm。10μm的間距能以這些技術設想。這使得改善因此獲得的KGRP之平板的本質良率是可能的。
此提供以RDL的KGRP平板接著其本身藉由較佳的液體附著劑7接合至KGRW晶圓之堆疊(圖3d)，例如借由環氧類型。
較佳的，依據變量(variant)，外部層202並未於原PCB平板之製造期間被建構(先前步驟)其因此僅包含內部層201。僅包含良好線路圖形之KGRP之暫時的平板係重建為如上所指示的。外部層202接著由在KGRP之暫時的平板之表面上生產RDL層(可選擇具有些許層)所取代(步驟c)，此RDL 30如上所指示般生產。這使得改 善因此獲得之KGRP平板的本質良率係為可能的。
此裝備以RDL層的KGRP平板接著其本身藉由較佳的液體附著劑7接合至KGRW晶圓之堆疊(步驟d，圖3d)，例如藉由環氧類型，並且因此形成「KGRW堆疊一PCB平板」組合件。
可選擇的，另一個KGRW堆疊係接合至KGRP平板，後者接著介於兩個KGRW之堆疊之間。更一般的來說，「KGRW堆疊一PCB平板」組合件可包含些許KGRW堆疊及/或些許KGRP平板，連續的互相接合，係如在圖4a之範例中所示。
未來3D模組係沿著垂直切割線9(在堆疊的方向上)進行切割(步驟e，圖3e)接著側向導體33形成在側面上(步驟f，圖3f)。較佳的，在切割步驟之前，黏皮8’置放於「KGRW堆疊一PCB平板」組合件之上以致能夠集體實行未來側面之金屬化步驟(步驟f)。此黏皮被移除以獲得3D模組。
當切割線9橫過玻璃纖維樹脂6’時(如能夠在圖4b之範例中所示)，在生產側向導體之前，這些纖維之剖面出現在3D電子模組的側面上。在此化學金屬化以生產這些側向導體33之時，接著沿著導致在蝕刻後之漏電流的這些纖維稍微滲入金屬化。由於在微珠之間未有連續，此載滿矽珠樹脂6之行為並不具有此缺點。藉由偏移切割線9至塗佈樹脂6之層級，在生產如圖4a所示之側向導體之前這些纖維之剖面並不出現在3D電子模組之側面上。
有些許PCB之類別，他們其中一些能有利的得到此變量的益處：
- 用於外部連接之PCB。這類6層PCB之佈線的範例(可能簡單的有他們中的10個)係如圖2a所示。在中央部分所見為矩陣針腳2’，其設計以接收主動組件的焊珠(solder bead)。4側支撐垂直於他們中之各者的導體且其在各種層之堆疊之後將沿著切割線進行切割：這些導體接著具有參考號204。這些導體具有例如介於100 μm與200 μm之間的間距。由於生產小於100 μm之間距於目前工業上以可接受的良率來說並不可實行，生產依據變量之RDL層係為大的值。
- 拓撲PCB，其係用以例如將存在於用於一個層級1之1或2側上之互連帶至存在於用於另一層級2之另一側之互連。圖5繪示在一側上具有輸出S1至S4之層級1與在兩側上再分配這些輸出之層級2互連之範例：輸出S1’及S2’再分配於側端2上，並且輸出S3’及S4’再分配於側端3上。
- 具有被動組件(電容器及/或電阻器及/或自電感器)之PCB通常由陶瓷做成，於表面安裝。圖6繪示自上述具有5個安裝被動組件所示之PCB的範例：一個電阻器R及4個電容器C。在此範例中，導體3’及204之間距是大的。其能夠以較大密度之被動組件而大大的減縮，被動組件像是例如在FPGA(Field Programmable Gate Array；場可程式化閘陣列)晶片之旁路的情形中之200個電容 器，對於FPGA晶片孤立電位接地及電源供應平面將需要對這些電容供電，側向輸出或是經由貫穿孔(through-hole)(TPV代表「貫穿聚合物導孔(Through Polymer Via)」)之輸出接著需要RDL層級。
- 具有陶瓷被動組件之PCB埋藏在此PCB中。此情況相同於先前的情況但是具有被動組件埋藏於PCB中。RDL層係用以取代在每個線路圖形之側(或是貫穿孔)的導體。
不考慮PCB類別，後者不包含矽。
某些主動堆疊(其具有快速處理器或具有大數目的輸入輸出之處理器，或是其它具有大匯流排的快速記憶體)需要些許電源供應電壓以及實際上不具有電感的電流分佈以致不延遲適當電壓準位的建立。
現存的解決方法在於生產貫穿孔或在晶片中的「貫穿矽導孔」之TSV以及在於將他們垂直互連，此垂直路徑短於通過3D模組側之者。然而，具有適當旁路之電源供應的問題需要使用盡可能的接近晶片之電容。
依據本發明，KGRP平板置放於KGRW堆疊上以致KGRW堆疊的RDL面朝PCB平板的RDL。亦可能的是，以下列方式進行。在接合步驟之後及在切割步驟之前，通過「KGRWs-KGRP平板之堆疊」組合件的開孔在樹脂中突穿並且填充以電性導電材料，像是藉由使用PCB技術的銅。這使得將在PCB中之電源供應平面與晶片之電源供應針腳透過TPV連接係為可能的，其導致介於75 μm 與200 μm之間的距離(其保持非常的小)。以這樣的方式連接的組合件在切割之前本身能在其它KGRW堆疊上及/或其它PCB平板上被堆疊。經由側向導體33之互連接著保留用於信號。
100‧‧‧堆疊
2‧‧‧連接元件
2’‧‧‧針腳
3‧‧‧導電走線
4‧‧‧基板
6‧‧‧樹脂
11‧‧‧組件
30‧‧‧再分配層
33‧‧‧導體
50‧‧‧薄片
200‧‧‧印刷電路板
3’‧‧‧導體
201‧‧‧內部層
202‧‧‧外部層
7‧‧‧液體附著劑
8‧‧‧附著基板
8’‧‧‧黏皮
9‧‧‧切割線
6’‧‧‧基板
S1-S4‧‧‧輸出
S1’-S4’‧‧‧輸出
本發明之其它特徵及優點在閱讀下列以非限定範例及參照所附圖式作成之詳細說明之後將變得更明白，其中：
圖1已說明表示依據前案之3D電子模組薄片之堆疊的示意性範例，圖2表示依據前案之PCB之示意性範例，由上述(圖2a)及剖面(圖2b)中所見，圖3闡述依據本發明用於3D電子模組之集體製造之各種步驟，圖4表示依據本發明3D電子模組之示意的兩個範例，一個沿著剖線以同樣的樹脂結構已進行切割(圖4a)，另一個則以兩個不同的樹脂結構(圖4b)，圖5表示依據前案，以分解的方式所示之PCB之拓撲範例，圖6表示依據前案，具有表面裝配被動組件之PCB的範例。
圖7表示PCB 200之平板的範例。
自一圖至其它圖之間，同樣的元件由同樣的參考所指示。

Claims (6)

  1. 一種3D電子模組之集體製造的方法，包含：- 製造重建晶圓之堆疊的步驟，製造N個重建晶圓之堆疊(100)，其中N1，所謂KGRW其各者只包含在電性測試後已驗證一致的線路圖形，一個線路圖形包含至少一個主動及/或被動矽組件(11)、至少一個包含主動組件的重建晶圓，此堆疊(100)包括一再分配層(30)，其具有最大4個互連層級，其特徵在於其包含：- 製造平板的步驟，製造只包含被動印刷電路(200)之一致的被動印刷電路之平板，該被動印刷電路包含至少6個互連層級且在測試後驗證，其包含下列子步驟：￮製造一致的印刷電路(200)之平板，￮每個印刷電路(200)之電性測試，￮在該測試後裝配已驗證的印刷電路至附著基板(8’)，￮鑄模安裝的電路於電性絕緣的環氧類型之樹脂(6)，所謂塗佈樹脂及樹脂之聚合，￮移除該附著基板(8’)，藉此於此步驟後獲得只包含已驗證印刷電路(200)的平板，所謂KGRP平板，- 接合步驟，將KGRP平板與KGRW堆疊(100)接合，為了形成「KGRWs-KGRP平板之堆疊」的組合件，- 切割步驟，沿著為了獲得3D電子模組之目的之切割線(9)切割「KGRWs-KGRP平板之堆疊」的組合件。
  2. 依據申請專利範圍第1項之3D電子模組之集體 製造的方法，其中其包含，介於該接合KRGP之步驟與該切割步驟之間，於KRGP之平板上生產具有厚度小於30 μm之再分配層(30)之步驟。
  3. 依據申請專利範圍第2項之3D電子模組之集體製造的方法，其中，該切割線(9)在該塗佈樹脂(6)上。
  4. 依據申請專利範圍第1項之3D電子模組之集體製造的方法，其中，由於該「KGRWs-KGRP平板之堆疊」的組合件在其厚度中包含至少一個電性絕緣區，其在該接合步驟與該切割步驟之間包含在該電性絕緣區中突穿開孔的步驟，以及包含以導電材料填充該些開孔的步驟。
  5. 依據申請專利範圍第1項之3D電子模組之集體製造的方法，其中製造些許KGRW堆疊(100)及/或些許KGRP平板，以及在該切割步驟之前，反覆將KGRW堆疊與KGRP平板接合之步驟，該「KGRWs-KGRPs平板之堆疊」組合件包含些許KGRW堆疊及/或些許KGRP平板。
  6. 依據申請專利範圍第5項之3D電子模組之集體製造的方法，其中印刷電路包含電阻器(R)及/或電容器(C)及/或自電感器。
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