JP2011139436A - 位相同期ループのジッタ検出方法及び装置 - Google Patents
位相同期ループのジッタ検出方法及び装置 Download PDFInfo
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- JP2011139436A JP2011139436A JP2010256931A JP2010256931A JP2011139436A JP 2011139436 A JP2011139436 A JP 2011139436A JP 2010256931 A JP2010256931 A JP 2010256931A JP 2010256931 A JP2010256931 A JP 2010256931A JP 2011139436 A JP2011139436 A JP 2011139436A
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- 238000000034 method Methods 0.000 title claims abstract description 5
- 238000001514 detection method Methods 0.000 claims abstract description 53
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 230000003111 delayed effect Effects 0.000 claims abstract description 11
- 230000010355 oscillation Effects 0.000 claims abstract description 11
- 239000000872 buffer Substances 0.000 claims description 6
- 230000001934 delay Effects 0.000 claims description 4
- 238000005259 measurement Methods 0.000 abstract description 5
- 238000012360 testing method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 239000011435 rock Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000005086 pumping Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
【解決手段】基準クロックとフィードバッククロックとの位相差信号を検出し、その位相差信号によって一定の周波数の発振信号を生成する位相同期ループと、入力遅延制御信号によって多数のキャパシタをスイッチングし、前記位相同期ループからの前記位相差信号を前記遅延制御信号によって遅延させる可変位相遅延部と、前記位相同期ループからの前記位相差信号と前記可変位相遅延部によって遅延された位相差信号とを比較し、前記位相差信号の遅延期間を検出する比較部と、前記比較部から検出された遅延期間以後にロック範囲内に位置することを検出するロック検出部とを備える。
【選択図】図1
Description
12 比較器
14 電荷ポンプ部
16 ループフィルタ
18 電圧制御発振器
20 分周器
30 ジッタ検出部
32、38、50 ノアゲート
34、40、42、62、64、66 インバータ
36 可変位相遅延部
46 ロック検出部
48 ロジック回路
Claims (6)
- 基準クロックとフィードバッククロックとの位相差信号を検出し、その位相差信号によって一定の周波数の発振信号を生成する位相同期ループと、
入力遅延制御信号によって多数のキャパシタをスイッチングし、前記位相同期ループからの前記位相差信号を前記遅延制御信号によって遅延させる可変位相遅延部と、
前記位相同期ループからの前記位相差信号と前記可変位相遅延部によって遅延された位相差信号とを比較し、前記位相差信号の遅延期間を検出する比較部と、
前記比較部から検出された遅延期間以後にロック範囲内に位置することを検出するロック検出部と
を備える位相同期ループのジッタ検出装置。 - 前記可変位相遅延部は、
入出力ラインに直列に接続された多数のインバータバッファと、
前記多数のインバータバッファの連結ラインに並列に接続された多数のキャパシタと、
前記遅延制御信号の各ビットに応答して前記多数のキャパシタをそれぞれスイッチングする多数のスィッチと
を備えることを特徴とする、請求項1に記載の位相同期ループのジッタ検出装置。 - 前記ロック範囲は、前記位相差信号の遅延時間に従って決定される
ことを特徴とする、請求項1または2に記載の位相同期ループのジッタ検出装置。 - 基準クロックとフィードバッククロックとの位相差信号を検出し、その位相差信号によって一定の周波数の発振信号を生成する段階と;
入力遅延制御信号によって多数のキャパシタをスイッチングし、前記位相差信号を前記遅延制御信号によって遅延させる段階と;
前記位相差信号と前記遅延された位相差信号とを比較し、前記位相差信号の遅延期間を検出する段階と;
前記検出された遅延期間以後にロック範囲内に位置することを検出するロック検出信号を生成するする段階と
を含む位相同期ループのジッタ検出方法。 - 前記遅延制御信号の各ビットに応答して前記多数のキャパシタをそれぞれスイッチングし、前記位相差信号の遅延時間を決定する
ことを特徴とする、請求項4に記載の位相同期ループのジッタ検出方法。 - 前記ロック範囲は、前記位相差信号の遅延時間に従って決定される
ことを特徴とする、請求項4または5に記載の位相同期ループのジッタ検出方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090135688A KR101264729B1 (ko) | 2009-12-31 | 2009-12-31 | 위상 동기 루프의 지터 검출 방법 및 장치 |
KR10-2009-0135688 | 2009-12-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011139436A true JP2011139436A (ja) | 2011-07-14 |
JP5112499B2 JP5112499B2 (ja) | 2013-01-09 |
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Application Number | Title | Priority Date | Filing Date |
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JP2010256931A Expired - Fee Related JP5112499B2 (ja) | 2009-12-31 | 2010-11-17 | 位相同期ループのジッタ検出装置 |
Country Status (4)
Country | Link |
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US (1) | US8179176B2 (ja) |
JP (1) | JP5112499B2 (ja) |
KR (1) | KR101264729B1 (ja) |
CN (1) | CN102118161B (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009278528A (ja) * | 2008-05-16 | 2009-11-26 | Elpida Memory Inc | Dll回路、および半導体装置 |
WO2012101776A1 (ja) * | 2011-01-26 | 2012-08-02 | 富士通株式会社 | 半導体装置、及び情報処理装置 |
CN102445698B (zh) * | 2011-11-07 | 2013-06-05 | 东南大学 | 一种gps接收机卫星跟踪失锁的判定方法 |
US9207705B2 (en) | 2012-11-07 | 2015-12-08 | Apple Inc. | Selectable phase or cycle jitter detector |
TWI503807B (zh) * | 2013-09-04 | 2015-10-11 | Mstar Semiconductor Inc | 運用於影像顯示的時序控制器及其控制方法 |
US9337848B2 (en) | 2014-02-27 | 2016-05-10 | Industry-Academic Cooperation Foundation, Yonsei University | Clock and data recovery device |
CN108318809B (zh) * | 2017-01-16 | 2020-09-01 | 奇景光电股份有限公司 | 频率抖动的内建自我测试电路 |
CN109120258B (zh) * | 2018-08-03 | 2022-03-15 | 北京大学深圳研究生院 | 一种温度自补偿环形振荡器和一种时钟产生电路 |
US11133920B2 (en) | 2019-09-03 | 2021-09-28 | Samsung Electronics Co., Ltd. | Clock and data recovery circuit and a display apparatus having the same |
CN114910733B (zh) * | 2022-07-15 | 2022-09-30 | 深圳益实科技有限公司 | 一种基于人工智能的显示器故障智能诊断分析系统 |
Citations (5)
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JPS6424630A (en) * | 1987-07-21 | 1989-01-26 | Yokogawa Electric Corp | Pll circuit |
JPH1174783A (ja) * | 1997-06-18 | 1999-03-16 | Mitsubishi Electric Corp | 内部クロック信号発生回路、および同期型半導体記憶装置 |
JPH11120768A (ja) * | 1997-10-09 | 1999-04-30 | Toshiba Corp | 半導体集積回路 |
JP2003258632A (ja) * | 2002-03-01 | 2003-09-12 | Fujitsu Ltd | ロック検出回路 |
WO2008088976A2 (en) * | 2007-01-11 | 2008-07-24 | International Business Machines Corporation | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
Family Cites Families (10)
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US5686864A (en) * | 1995-09-05 | 1997-11-11 | Motorola, Inc. | Method and apparatus for controlling a voltage controlled oscillator tuning range in a frequency synthesizer |
US6812754B1 (en) * | 2000-06-05 | 2004-11-02 | Renesas Technology Corp. | Clock synchronizer with offset prevention function against variation of output potential of loop filter |
US6831523B1 (en) * | 2000-07-10 | 2004-12-14 | Silicon Laboratories Inc. | Auto-detection between referenceless and reference clock mode of operation |
KR100630342B1 (ko) * | 2004-07-27 | 2006-09-29 | 삼성전자주식회사 | 락 검출기능을 구비한 위상동기루프 회로 및 위상동기루프회로의 락 검출방법 |
US7742554B2 (en) * | 2006-07-10 | 2010-06-22 | Mediatek Inc. | PLL device with leakage current compensation unit |
US8076979B2 (en) * | 2008-04-04 | 2011-12-13 | Freescale Semiconductor, Inc. | Lock detection circuit for phase locked loop |
KR101020513B1 (ko) * | 2008-09-04 | 2011-03-09 | 한국전자통신연구원 | 락 검출 회로 및 락 검출 방법 |
KR101231743B1 (ko) * | 2009-04-24 | 2013-02-08 | 한국전자통신연구원 | 디지털 락 검출장치 및 이를 포함하는 주파수 합성기 |
KR101631164B1 (ko) * | 2010-03-18 | 2016-06-16 | 삼성전자주식회사 | 위상 동기 루프 회로, 락 검출 방법 및 이를 포함한 시스템 |
US8222933B2 (en) * | 2010-05-07 | 2012-07-17 | Texas Instruments Incorporated | Low power digital phase lock loop circuit |
-
2009
- 2009-12-31 KR KR1020090135688A patent/KR101264729B1/ko active IP Right Grant
-
2010
- 2010-08-10 US US12/853,704 patent/US8179176B2/en not_active Expired - Fee Related
- 2010-09-28 CN CN201010502816.6A patent/CN102118161B/zh not_active Expired - Fee Related
- 2010-11-17 JP JP2010256931A patent/JP5112499B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6424630A (en) * | 1987-07-21 | 1989-01-26 | Yokogawa Electric Corp | Pll circuit |
JPH1174783A (ja) * | 1997-06-18 | 1999-03-16 | Mitsubishi Electric Corp | 内部クロック信号発生回路、および同期型半導体記憶装置 |
JPH11120768A (ja) * | 1997-10-09 | 1999-04-30 | Toshiba Corp | 半導体集積回路 |
JP2003258632A (ja) * | 2002-03-01 | 2003-09-12 | Fujitsu Ltd | ロック検出回路 |
WO2008088976A2 (en) * | 2007-01-11 | 2008-07-24 | International Business Machines Corporation | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
Also Published As
Publication number | Publication date |
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US20110156780A1 (en) | 2011-06-30 |
CN102118161A (zh) | 2011-07-06 |
KR20110078790A (ko) | 2011-07-07 |
CN102118161B (zh) | 2016-09-28 |
KR101264729B1 (ko) | 2013-05-15 |
US8179176B2 (en) | 2012-05-15 |
JP5112499B2 (ja) | 2013-01-09 |
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