JP2011061457A - クロック生成回路及びこれを備える半導体装置並びにデータ処理システム - Google Patents

クロック生成回路及びこれを備える半導体装置並びにデータ処理システム Download PDF

Info

Publication number
JP2011061457A
JP2011061457A JP2009208455A JP2009208455A JP2011061457A JP 2011061457 A JP2011061457 A JP 2011061457A JP 2009208455 A JP2009208455 A JP 2009208455A JP 2009208455 A JP2009208455 A JP 2009208455A JP 2011061457 A JP2011061457 A JP 2011061457A
Authority
JP
Japan
Prior art keywords
circuit
signal
operation mode
clock signal
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2009208455A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011061457A5 (enExample
Inventor
Kazutaka Miyano
和孝 宮野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Priority to JP2009208455A priority Critical patent/JP2011061457A/ja
Priority to US12/805,652 priority patent/US9007861B2/en
Priority to KR1020100082275A priority patent/KR101138028B1/ko
Publication of JP2011061457A publication Critical patent/JP2011061457A/ja
Publication of JP2011061457A5 publication Critical patent/JP2011061457A5/ja
Priority to US14/679,450 priority patent/US9438251B2/en
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2009208455A 2009-09-09 2009-09-09 クロック生成回路及びこれを備える半導体装置並びにデータ処理システム Ceased JP2011061457A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009208455A JP2011061457A (ja) 2009-09-09 2009-09-09 クロック生成回路及びこれを備える半導体装置並びにデータ処理システム
US12/805,652 US9007861B2 (en) 2009-09-09 2010-08-11 Clock generating circuit, semiconductor device including the same, and data processing system
KR1020100082275A KR101138028B1 (ko) 2009-09-09 2010-08-25 클럭 생성 회로, 이를 포함하는 반도체 디바이스, 및 데이터 프로세싱 시스템
US14/679,450 US9438251B2 (en) 2009-09-09 2015-04-06 Clock generating circuit, semiconductor device including the same, and data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009208455A JP2011061457A (ja) 2009-09-09 2009-09-09 クロック生成回路及びこれを備える半導体装置並びにデータ処理システム

Publications (2)

Publication Number Publication Date
JP2011061457A true JP2011061457A (ja) 2011-03-24
JP2011061457A5 JP2011061457A5 (enExample) 2012-08-16

Family

ID=43647683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009208455A Ceased JP2011061457A (ja) 2009-09-09 2009-09-09 クロック生成回路及びこれを備える半導体装置並びにデータ処理システム

Country Status (3)

Country Link
US (2) US9007861B2 (enExample)
JP (1) JP2011061457A (enExample)
KR (1) KR101138028B1 (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8769194B2 (en) 2011-07-28 2014-07-01 Hiroki Fujisawa Information processing system including semiconductor device having self-refresh mode
WO2014112509A1 (ja) * 2013-01-16 2014-07-24 ピーエスフォー ルクスコ エスエイアールエル 出力信号生成装置、半導体装置および出力信号生成方法
US8811105B2 (en) 2011-07-28 2014-08-19 Ps4 Luxco S.A.R.L. Information processing system including semiconductor device having self-refresh mode
JP2021120909A (ja) * 2017-06-30 2021-08-19 ルネサスエレクトロニクス株式会社 半導体集積回路
JP2021182658A (ja) * 2020-05-18 2021-11-25 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. 遅延ロックループデバイス及びその更新方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7656745B2 (en) 2007-03-15 2010-02-02 Micron Technology, Inc. Circuit, system and method for controlling read latency
US8604850B2 (en) 2011-03-29 2013-12-10 Micron Technology, Inc. Measurement initialization circuitry
JP5932237B2 (ja) 2011-04-20 2016-06-08 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
JP2013183415A (ja) * 2012-03-05 2013-09-12 Elpida Memory Inc 半導体装置及びクロック信号の位相調整方法
KR101957814B1 (ko) * 2012-06-13 2019-03-14 에스케이하이닉스 주식회사 집적 회로 및 이의 동작 방법
KR20140012312A (ko) * 2012-07-19 2014-02-03 에스케이하이닉스 주식회사 지연 고정 루프 회로 및 그의 구동 방법
JP2015008029A (ja) 2013-06-26 2015-01-15 マイクロン テクノロジー， インク． 半導体装置
KR102099406B1 (ko) * 2013-12-30 2020-04-09 에스케이하이닉스 주식회사 반도체 장치
US9813067B2 (en) 2015-06-10 2017-11-07 Micron Technology, Inc. Clock signal and supply voltage variation tracking
KR20170049193A (ko) * 2015-10-28 2017-05-10 삼성전자주식회사 지연 고정 루프회로 및 이를 포함하는 반도체 메모리 장치
KR102405066B1 (ko) * 2015-12-23 2022-06-07 에스케이하이닉스 주식회사 신호 쉬프팅 회로, 베이스 칩 및 이를 포함하는 반도체 시스템
US9865317B2 (en) 2016-04-26 2018-01-09 Micron Technology, Inc. Methods and apparatuses including command delay adjustment circuit
US9997220B2 (en) * 2016-08-22 2018-06-12 Micron Technology, Inc. Apparatuses and methods for adjusting delay of command signal path
US10761559B2 (en) * 2016-12-13 2020-09-01 Qualcomm Incorporated Clock gating enable generation
US10224938B2 (en) 2017-07-26 2019-03-05 Micron Technology, Inc. Apparatuses and methods for indirectly detecting phase variations
KR102536639B1 (ko) 2018-08-14 2023-05-26 에스케이하이닉스 주식회사 메모리 장치의 버퍼 제어 회로
US10892002B2 (en) 2018-10-24 2021-01-12 Micron Technology, Inc. Selectively controlling clock transmission to a data (DQ) system
KR20230083929A (ko) * 2021-12-03 2023-06-12 에스케이하이닉스 주식회사 샘플링 회로를 포함하는 집적 회로 및 메모리 장치
CN116072177B (zh) * 2023-03-14 2023-06-16 长鑫存储技术有限公司 一种存储器

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11219587A (ja) * 1998-02-03 1999-08-10 Fujitsu Ltd 半導体装置
JP2000163963A (ja) * 1998-11-27 2000-06-16 Fujitsu Ltd セルフタイミング制御回路を内蔵する集積回路装置
JP2001118385A (ja) * 1999-10-19 2001-04-27 Nec Corp 遅延同期ループの同期方法、遅延同期ループ及び該遅延同期ループを備えた半導体装置
JP2001195149A (ja) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp 内部クロック信号発生回路
JP2002184864A (ja) * 2000-10-03 2002-06-28 Mitsubishi Electric Corp 半導体装置
JP2002324369A (ja) * 2001-02-26 2002-11-08 Sony Corp ディレイロックループ回路、可変遅延回路および記録信号補償回路
JP2003110423A (ja) * 2001-09-20 2003-04-11 Hynix Semiconductor Inc 混合型遅延固定ループ回路及びそのクロック信号同期方法
JP2004222276A (ja) * 2003-01-09 2004-08-05 Hynix Semiconductor Inc トラッキングアナログ−デジタル変換器を備えるアナログ遅延固定ループ及びアナログ位相固定ループ
JP2007097135A (ja) * 2005-09-29 2007-04-12 Hynix Semiconductor Inc ロックフェイル防止のための遅延固定ループクロックの生成方法及びその装置
JP2007115307A (ja) * 2005-10-18 2007-05-10 Elpida Memory Inc 半導体記憶装置
JP2008154199A (ja) * 2006-11-24 2008-07-03 Matsushita Electric Ind Co Ltd クロック制御回路
JP2009105657A (ja) * 2007-10-23 2009-05-14 Elpida Memory Inc Ｄｌｌ回路及びこれを備える半導体装置、並びに、データ処理システム

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6088255A (en) * 1998-03-20 2000-07-11 Fujitsu Limited Semiconductor device with prompt timing stabilization
JP3807593B2 (ja) * 2000-07-24 2006-08-09 株式会社ルネサステクノロジ クロック生成回路および制御方法並びに半導体記憶装置
US6456130B1 (en) * 2001-01-11 2002-09-24 Infineon Technologies Ag Delay lock loop and update method with limited drift and improved power savings
US6628154B2 (en) * 2001-07-31 2003-09-30 Cypress Semiconductor Corp. Digitally controlled analog delay locked loop (DLL)
US6646942B2 (en) * 2001-10-09 2003-11-11 Micron Technology, Inc. Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages
JP4104886B2 (ja) * 2002-03-20 2008-06-18 株式会社ルネサステクノロジ 半導体装置
KR100493054B1 (ko) * 2003-03-04 2005-06-02 삼성전자주식회사 지연동기 루프를 구비하는 반도체 장치 및 지연동기 루프제어방법
JP4276112B2 (ja) 2003-03-04 2009-06-10 三星電子株式会社 遅延同期ループ回路及び遅延同期ループ制御回路を備える半導体装置並びに前記遅延同期ループ回路を制御する方法
WO2005042804A2 (en) * 2003-10-22 2005-05-12 Nexx Systems, Inc. Method and apparatus for fluid processing a workpiece
JP2005292947A (ja) 2004-03-31 2005-10-20 Hitachi Ltd データ処理装置、遅延回路及び遅延素子
US8144529B2 (en) * 2009-03-31 2012-03-27 Intel Corporation System and method for delay locked loop relock mode

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11219587A (ja) * 1998-02-03 1999-08-10 Fujitsu Ltd 半導体装置
JP2000163963A (ja) * 1998-11-27 2000-06-16 Fujitsu Ltd セルフタイミング制御回路を内蔵する集積回路装置
JP2001118385A (ja) * 1999-10-19 2001-04-27 Nec Corp 遅延同期ループの同期方法、遅延同期ループ及び該遅延同期ループを備えた半導体装置
JP2001195149A (ja) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp 内部クロック信号発生回路
JP2002184864A (ja) * 2000-10-03 2002-06-28 Mitsubishi Electric Corp 半導体装置
JP2002324369A (ja) * 2001-02-26 2002-11-08 Sony Corp ディレイロックループ回路、可変遅延回路および記録信号補償回路
JP2003110423A (ja) * 2001-09-20 2003-04-11 Hynix Semiconductor Inc 混合型遅延固定ループ回路及びそのクロック信号同期方法
JP2004222276A (ja) * 2003-01-09 2004-08-05 Hynix Semiconductor Inc トラッキングアナログ−デジタル変換器を備えるアナログ遅延固定ループ及びアナログ位相固定ループ
JP2007097135A (ja) * 2005-09-29 2007-04-12 Hynix Semiconductor Inc ロックフェイル防止のための遅延固定ループクロックの生成方法及びその装置
JP2007115307A (ja) * 2005-10-18 2007-05-10 Elpida Memory Inc 半導体記憶装置
JP2008154199A (ja) * 2006-11-24 2008-07-03 Matsushita Electric Ind Co Ltd クロック制御回路
JP2009105657A (ja) * 2007-10-23 2009-05-14 Elpida Memory Inc Ｄｌｌ回路及びこれを備える半導体装置、並びに、データ処理システム

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8769194B2 (en) 2011-07-28 2014-07-01 Hiroki Fujisawa Information processing system including semiconductor device having self-refresh mode
US8811105B2 (en) 2011-07-28 2014-08-19 Ps4 Luxco S.A.R.L. Information processing system including semiconductor device having self-refresh mode
WO2014112509A1 (ja) * 2013-01-16 2014-07-24 ピーエスフォー ルクスコ エスエイアールエル 出力信号生成装置、半導体装置および出力信号生成方法
JP2021120909A (ja) * 2017-06-30 2021-08-19 ルネサスエレクトロニクス株式会社 半導体集積回路
JP7075528B2 (ja) 2017-06-30 2022-05-25 ルネサスエレクトロニクス株式会社 半導体集積回路
JP2021182658A (ja) * 2020-05-18 2021-11-25 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. 遅延ロックループデバイス及びその更新方法

Also Published As

Publication number Publication date
US20150214962A1 (en) 2015-07-30
KR101138028B1 (ko) 2012-04-20
US9007861B2 (en) 2015-04-14
US20110058437A1 (en) 2011-03-10
US9438251B2 (en) 2016-09-06
KR20110027567A (ko) 2011-03-16

Similar Documents

Publication Publication Date Title
JP2011061457A (ja) クロック生成回路及びこれを備える半導体装置並びにデータ処理システム
US8773943B2 (en) Semiconductor device outputting read data in synchronization with clock signal
US8953409B2 (en) Semiconductor device capable of minimizing mutual effects between two different operations therein
US9077350B2 (en) Delay-locked loop circuit and method of controlling the same
US8487671B2 (en) Internal-clock adjusting circuit
US6975556B2 (en) Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
JP2011060385A (ja) 半導体装置及びその制御方法並びにデータ処理システム
JP2010088108A (ja) Ｄｌｌ回路及びその制御方法
JP2011060364A (ja) クロック生成回路及びこれを備える半導体装置並びにデータ処理システム
JP2012252733A (ja) 半導体装置
US8509024B2 (en) Semiconductor device having plural internal voltage generating circuits and method of controlling the same
US7423456B2 (en) Fast response time, low power phase detector circuits, devices and systems incorporating the same, and associated methods
US7139345B2 (en) Method and circuit for adjusting the timing of output data based on the current and future states of the output data
US9473146B2 (en) Apparatuses and methods for low power counting circuits
US9065456B2 (en) Semiconductor device having DLL circuit
US11120855B2 (en) Semiconductor device including a clock adjustment circuit
KR100550633B1 (ko) 반도체 기억 소자의 지연 고정 루프 및 그의 제어 방법
JP2012094205A (ja) 半導体装置
JP2014158200A (ja) 半導体装置
JP2013093513A (ja) 半導体装置
WO2014115657A1 (ja) 出力信号生成装置、半導体装置および出力信号生成方法

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120703

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120703

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20130730

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130822

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140114

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140401

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140404

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140714

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150127

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150413

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150512

A045 Written measure of dismissal of application [lapsed due to lack of payment]

Free format text: JAPANESE INTERMEDIATE CODE: A045

Effective date: 20150929