JP2010525599A - エピタキシャル層を移動させる方法 - Google Patents
エピタキシャル層を移動させる方法 Download PDFInfo
- Publication number
- JP2010525599A JP2010525599A JP2010504889A JP2010504889A JP2010525599A JP 2010525599 A JP2010525599 A JP 2010525599A JP 2010504889 A JP2010504889 A JP 2010504889A JP 2010504889 A JP2010504889 A JP 2010504889A JP 2010525599 A JP2010525599 A JP 2010525599A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- intermediate layer
- epitaxial layer
- melting temperature
- donor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 230000008018 melting Effects 0.000 claims abstract description 65
- 238000002844 melting Methods 0.000 claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 claims abstract description 58
- 238000010438 heat treatment Methods 0.000 claims abstract description 28
- 238000000926 separation method Methods 0.000 claims abstract description 28
- 238000000407 epitaxy Methods 0.000 claims abstract description 10
- 229910052732 germanium Inorganic materials 0.000 claims description 32
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 32
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 22
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 5
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 claims description 4
- 238000005728 strengthening Methods 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 12
- 238000005516 engineering process Methods 0.000 description 6
- 230000033001 locomotion Effects 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910002601 GaN Inorganic materials 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229910017214 AsGa Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 239000001993 wax Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
‐ドナー基板及び中間層は、シリコンゲルマニウムから形成され、中間層内のゲルマニウム濃度は、ドナー基板内のゲルマニウム濃度より高く、
‐エピタキシャル層は、前述の中間層上で歪シリコン(sSI)層の成長によって形成される。
‐ドナー基板は、二酸化シリコン層で覆われたシリコンから形成され、
‐中間層は、ゲルマニウムから形成され、
‐エピタキシャル層は、ガリウムヒ素から形成される。
‐ドナー基板は、サファイアから形成され、
‐中間層は、窒化インジウム(InN)から形成され
‐エピタキシャル層は、窒化ガリウム(GaN)から形成される。
‐基板31は、0から20%まで増加するゲルマニウム濃度を有するSiGe層であり、
‐中間層32は、60%に等しいゲルマニウム濃度を有するSiGe層であり、
‐エピタキシャル層32は、20%に等しいゲルマニウム濃度を有するSiGe層である。
‐ドナー基板41は、0から20%まで増加する濃度を有するシリコンゲルマニウムにより形成され、
‐中間層42は、60%に等しいゲルマニウム濃度を有するシリコンゲルマニウム層であり、
‐スペーサ層41’と42’は、20%に等しいゲルマニウム濃度を有するシリコンゲルマニウム層である。これらのスペーサ層は、構造410の異なる層の格子定数を安定させる役割を有する。
‐二酸化シリコン層で覆われたシリコンドナー基板51、
‐GeOI構造の最上層である、融解温度がTf(52)=937℃であるゲルマニウムの中間層52、
‐中間層52上の擬似エピタキシーによって形成され、融解温度Tf(53)=1240℃を有するガリウムヒ素のエピタキシャル層53
を備える。
この方法で製造される構造510は、次いで、二酸化シリコンSiO2の層54で覆われたシリコン支持基板55上に接合される。分離後、AsGAOI構造が得られる。
Claims (14)
- エピタキシャル層(3;33;43;53)を生成する方法であって、
ドナー基板(1;31;41;51)上の中間層(2;32;42;52)の形成(S1)と、
エピタキシーによる前記中間層(2;32;42;52)上の前記エピタキシャル層(3;33;43;53)の形成(S2)と
を備える構造(10;310;410;510)の製造ステップであって、前記中間層(2;32;42;52)の融解温度(Tf(32);Tf(42))は、前記エピタキシャル層(3;33;43;53)の融解温度(Tf(33);Tf(43))より低い製造ステップ、及び
少なくとも1回の熱処理を得られる前記構造(10;310;410;510)に適用すること(S4)による、前記ドナー基板(1;31;41;51)からの前記エピタキシャル層(3;33;43;53)の分離ステップ(S5)であって、この熱処理は、前記中間層(2;32;42;52)の前記融解温度(Tf(32);Tf(42))と、前記エピタキシャル層(3;33;43;53)の前記融解温度(Tf(33);Tf(43))との間から成る温度で実行される分離ステップ
を備えることを特徴とする方法。 - 請求項1に記載の生成方法において、製造ステップの前且つ分離ステップ(S5)の後に、支持基板(5;55)への前記エピタキシャル層(3;33;43;53)のボンディングステップ(S3)を更に備えることを特徴とする方法。
- 請求項2に記載の生成方法において、前記エピタキシャル層(3;53)が接合される前記支持基板(5;55)は、その表面に酸化層(4;54)を備えることを特徴とする方法。
- 請求項2又は3に記載の生成方法において、前記ボンディングステップ(S3)は、分子ボンディングにより実行されることを特徴とする方法。
- 請求項1乃至4のうちの何れか1つに記載の生成方法において、前記分離ステップ(S4)において、前記熱処理と同時に機械的分離力が適用されることを特徴とする方法。
- 請求項2乃至5のうちの何れか1つに記載の生成方法において、前記ボンディングステップ(S3)に続いて、前記ボンディングの表面を強化する熱処理ステップがあることを特徴とする方法。
- 請求項1乃至6のうちの何れか1つに記載の生成方法において、分離されたエピタキシャル層(3)上に残っている中間層(2)の残余物(6)の除去ステップ(S6)を更に備えることを特徴とする方法。
- 請求項1乃至7のうちの何れか1つに記載の生成方法において、前記製造ステップ(S2)の間、前記中間層(2)は、前記ドナー基板(1)上にエピタキシーにより形成されることを特徴とする方法。
- 請求項1乃至7のうちの何れか1つに記載の生成方法において、前記製造ステップの間、前記中間層(52)及びドナー基板(51)は、SeOI構造から形成されることを特徴とする方法。
- 請求項1乃至7のうちの何れか1つに記載の生成方法において、前記製造ステップの間、前記中間層(42)及びエピタキシャル層(43)は、シリコンゲルマニウムから形成され、前記中間層(42)は、前記エピタキシャル層(43)のゲルマニウム濃度より高いゲルマニウム濃度を有して形成され、これにより前記中間層(42)の前記融解温度(Tf(42))は、前記エピタキシャル層(43)の前記融解温度(Tf(43))より低いことを特徴とする方法。
- 請求項1乃至7のうちの何れか1つに記載の生成方法において、前記製造ステップの間、
‐前記ドナー基板(31)及び中間層(32)は、シリコンゲルマニウムから形成され、前記中間層内のゲルマニウム濃度は、前記ドナー基板内のゲルマニウム濃度より高く、
‐前記エピタキシャル層(33)は、前記中間層上の歪シリコン(sSI)層の成長により形成される
ことを特徴とする方法。 - 請求項10又は11に記載の生成方法において、前記製造ステップの間、前記ドナー基板(31’;41’)と前記中間層(42’)との間、及び/又は、前記中間層(32;42)と前記エピタキシャル(33;43)層との間に、少なくとも一つのスペーサ層(31’;41’;42’)が形成されることを特徴とする方法。
- 請求項1乃至7のうちの何れか1つに記載の生成方法において、前記製造ステップの間、
‐前記ドナー基板(51)は、二酸化シリコン層で覆われたシリコンから形成され、
‐前記中間層(52)は、ゲルマニウムから形成され、
‐前記エピタキシャル層(53)は、ガリウムヒ素から形成される
ことを特徴とする方法。 - 請求項1乃至7のうちの何れか1つに記載の生成方法において、前記製造ステップの間、
‐前記ドナー基板(1)は、サファイアから形成され、
‐前記中間層(2)は、窒化インジウム(InN)から形成され、
‐前記エピタキシャル層(3)は、窒化ガリウム(GaN)から形成される
ことを特徴とする方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0754777A FR2915625B1 (fr) | 2007-04-27 | 2007-04-27 | Procede de transfert d'une couche epitaxiale |
FR0754777 | 2007-04-27 | ||
PCT/IB2008/000967 WO2008132569A1 (en) | 2007-04-27 | 2008-04-15 | Method for transferring an epitaxial layer |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010525599A true JP2010525599A (ja) | 2010-07-22 |
JP5380429B2 JP5380429B2 (ja) | 2014-01-08 |
Family
ID=39212207
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010504889A Active JP5380429B2 (ja) | 2007-04-27 | 2008-04-15 | エピタキシャル層を移動させる方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7981768B2 (ja) |
EP (1) | EP2140488A1 (ja) |
JP (1) | JP5380429B2 (ja) |
KR (1) | KR101527063B1 (ja) |
CN (1) | CN101636833B (ja) |
FR (1) | FR2915625B1 (ja) |
WO (1) | WO2008132569A1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2467935B (en) * | 2009-02-19 | 2013-10-30 | Iqe Silicon Compounds Ltd | Formation of thin layers of GaAs and germanium materials |
US8492325B2 (en) | 2010-03-01 | 2013-07-23 | The Procter & Gamble Company | Dual-usage liquid laundry detergents comprising a silicone anti-foam |
DE102010046215B4 (de) * | 2010-09-21 | 2019-01-03 | Infineon Technologies Austria Ag | Halbleiterkörper mit verspanntem Bereich, Elektronisches Bauelement und ein Verfahren zum Erzeugen des Halbleiterkörpers. |
KR20140128393A (ko) * | 2012-02-07 | 2014-11-05 | 더 리젠츠 오브 더 유니버시티 오브 미시간 | 에피택셜 리프트 오프 후 웨이퍼 재사용을 위한 열 표면 처리 |
US9257339B2 (en) * | 2012-05-04 | 2016-02-09 | Silicon Genesis Corporation | Techniques for forming optoelectronic devices |
CN103839976A (zh) * | 2012-11-27 | 2014-06-04 | 中国科学院微电子研究所 | 一种硅基绝缘体上砷化镓衬底结构及其制备方法 |
US9064789B2 (en) | 2013-08-12 | 2015-06-23 | International Business Machines Corporation | Bonded epitaxial oxide structures for compound semiconductor on silicon substrates |
JP2015065241A (ja) * | 2013-09-24 | 2015-04-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
DE102013020693A1 (de) * | 2013-12-04 | 2015-06-11 | Siltectra Gmbh | Verfahren zum Erzeugen großflächiger Festkörperschichten |
CN108598218B (zh) * | 2018-04-26 | 2020-08-11 | 上海空间电源研究所 | 一种外延层刚性-柔性衬底无机键合转移方法 |
CN109545999B (zh) * | 2018-11-21 | 2021-05-04 | 京东方科技集团股份有限公司 | 初始显示装置和柔性显示面板的制造方法 |
CN111893566A (zh) * | 2020-07-21 | 2020-11-06 | 璨隆科技发展有限公司 | 一种氮化镓晶体的制备方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998009333A1 (en) * | 1996-08-27 | 1998-03-05 | Seiko Epson Corporation | Separating method, method for transferring thin film device, thin film device, thin film integrated circuit device, and liquid crystal display device manufactured by using the transferring method |
WO2002082514A1 (en) * | 2001-04-04 | 2002-10-17 | Massachusetts Institute Of Technology | A method for semiconductor device fabrication |
JP2003034599A (ja) * | 2001-04-13 | 2003-02-07 | Matsushita Electric Ind Co Ltd | Iii族窒化物半導体基板の製造方法 |
JP2006287166A (ja) * | 2005-04-05 | 2006-10-19 | Advanced Lcd Technologies Development Center Co Ltd | 半導体素子保持装置、半導体素子の剥離方法および表示装置 |
JP2006344865A (ja) * | 2005-06-10 | 2006-12-21 | Toyoko Kagaku Co Ltd | Soi基板及び該基板の製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JP3112106B2 (ja) * | 1991-10-11 | 2000-11-27 | キヤノン株式会社 | 半導体基材の作製方法 |
DE19640594B4 (de) * | 1996-10-01 | 2016-08-04 | Osram Gmbh | Bauelement |
US6210479B1 (en) * | 1999-02-26 | 2001-04-03 | International Business Machines Corporation | Product and process for forming a semiconductor structure on a host substrate |
JP2002110949A (ja) * | 2000-09-28 | 2002-04-12 | Canon Inc | Soiの熱処理方法及び製造方法 |
US6723165B2 (en) * | 2001-04-13 | 2004-04-20 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating Group III nitride semiconductor substrate |
ATE393473T1 (de) * | 2004-06-11 | 2008-05-15 | Soitec Silicon On Insulator | Verfahren zur herstellung eines verbundsubstrats |
US7608471B2 (en) * | 2005-08-09 | 2009-10-27 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method and apparatus for integrating III-V semiconductor devices into silicon processes |
-
2007
- 2007-04-27 FR FR0754777A patent/FR2915625B1/fr active Active
-
2008
- 2008-04-15 CN CN2008800066321A patent/CN101636833B/zh active Active
- 2008-04-15 EP EP08737488A patent/EP2140488A1/en not_active Withdrawn
- 2008-04-15 JP JP2010504889A patent/JP5380429B2/ja active Active
- 2008-04-15 KR KR1020097018793A patent/KR101527063B1/ko active IP Right Grant
- 2008-04-15 WO PCT/IB2008/000967 patent/WO2008132569A1/en active Application Filing
- 2008-04-15 US US12/528,573 patent/US7981768B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998009333A1 (en) * | 1996-08-27 | 1998-03-05 | Seiko Epson Corporation | Separating method, method for transferring thin film device, thin film device, thin film integrated circuit device, and liquid crystal display device manufactured by using the transferring method |
WO2002082514A1 (en) * | 2001-04-04 | 2002-10-17 | Massachusetts Institute Of Technology | A method for semiconductor device fabrication |
JP2003034599A (ja) * | 2001-04-13 | 2003-02-07 | Matsushita Electric Ind Co Ltd | Iii族窒化物半導体基板の製造方法 |
JP2006287166A (ja) * | 2005-04-05 | 2006-10-19 | Advanced Lcd Technologies Development Center Co Ltd | 半導体素子保持装置、半導体素子の剥離方法および表示装置 |
JP2006344865A (ja) * | 2005-06-10 | 2006-12-21 | Toyoko Kagaku Co Ltd | Soi基板及び該基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP2140488A1 (en) | 2010-01-06 |
KR20100014953A (ko) | 2010-02-11 |
CN101636833B (zh) | 2011-06-08 |
US7981768B2 (en) | 2011-07-19 |
WO2008132569A1 (en) | 2008-11-06 |
US20110008948A1 (en) | 2011-01-13 |
KR101527063B1 (ko) | 2015-06-08 |
CN101636833A (zh) | 2010-01-27 |
FR2915625B1 (fr) | 2009-10-02 |
JP5380429B2 (ja) | 2014-01-08 |
FR2915625A1 (fr) | 2008-10-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5380429B2 (ja) | エピタキシャル層を移動させる方法 | |
KR100746182B1 (ko) | 합성재료 웨이퍼의 제조 방법 | |
JP5462289B2 (ja) | 熱膨張係数が局所的に適合するヘテロ構造の生成方法 | |
US8105916B2 (en) | Relaxation and transfer of strained layers | |
JP4733633B2 (ja) | エピタキシャル基板の製造方法 | |
KR20060017615A (ko) | 유용층에 의해 덮혀진 한 쌍의 기판을 동시에 얻는 방법 | |
FR3030877B1 (fr) | Fabrication de couches de nitrure de groupe iiia sur structures de semi-conducteur sur isolant | |
US10115698B2 (en) | Method for direct adhesion via low-roughness metal layers | |
US20200303243A1 (en) | Method for manufacturing semiconductor structure | |
CN109585615B (zh) | 将氮化镓外延层从衬底上剥离的方法 | |
JP4866935B2 (ja) | 立方晶炭化ケイ素単結晶薄膜の製造方法及び半導体装置 | |
US20050048736A1 (en) | Methods for adhesive transfer of a layer | |
JP2010502555A (ja) | GaN基板の製造方法 | |
WO2016080506A1 (ja) | ウエハの接合方法 | |
CN113841223B (zh) | 半导体基板的制造方法和半导体装置的制造方法 | |
JP2019528570A (ja) | 成長基板上にエピタキシャル層を生成する方法 | |
JP5931803B2 (ja) | 窒化物半導体装置の製造方法 | |
US10242915B2 (en) | Method for transferring at least one thin film | |
JP2008532328A (ja) | 半導体材料の少なくとも1つの厚い層を含むヘテロ構造の製造方法 | |
WO2019087157A1 (en) | Layer transfer of epitaxial layers and thin films obtained by van der waals growth initiation | |
KR20130051232A (ko) | 박막 접합 기판 및 그 제조방법 | |
US10792904B2 (en) | Method for bonding one component to another component | |
US20230110410A1 (en) | Method for manufacturing components on both faces of a substrate | |
CN112740359B (zh) | 半导体元件的制造方法及半导体基板 | |
JP2023519166A (ja) | 積層構造を製造するための方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110316 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130329 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130621 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130628 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130729 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130830 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130930 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5380429 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |