JP2010524237A5 - - Google Patents

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Publication number
JP2010524237A5
JP2010524237A5 JP2010502176A JP2010502176A JP2010524237A5 JP 2010524237 A5 JP2010524237 A5 JP 2010524237A5 JP 2010502176 A JP2010502176 A JP 2010502176A JP 2010502176 A JP2010502176 A JP 2010502176A JP 2010524237 A5 JP2010524237 A5 JP 2010524237A5
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JP
Japan
Prior art keywords
layer
dielectric
gap filling
forming
dielectric gap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010502176A
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English (en)
Japanese (ja)
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JP2010524237A (ja
Filing date
Publication date
Priority claimed from US11/697,106 external-priority patent/US8435898B2/en
Application filed filed Critical
Publication of JP2010524237A publication Critical patent/JP2010524237A/ja
Publication of JP2010524237A5 publication Critical patent/JP2010524237A5/ja
Pending legal-status Critical Current

Links

JP2010502176A 2007-04-05 2008-03-12 不揮発性メモリの第１層間誘電体スタック Pending JP2010524237A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/697,106 US8435898B2 (en) 2007-04-05 2007-04-05 First inter-layer dielectric stack for non-volatile memory
PCT/US2008/056562 WO2008124240A1 (en) 2007-04-05 2008-03-12 A first inter-layer dielectric stack for non-volatile memory

Publications (2)

Publication Number Publication Date
JP2010524237A JP2010524237A (ja) 2010-07-15
JP2010524237A5 true JP2010524237A5 (enExample) 2011-04-21

Family

ID=39827325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010502176A Pending JP2010524237A (ja) 2007-04-05 2008-03-12 不揮発性メモリの第１層間誘電体スタック

Country Status (7)

Country Link
US (1) US8435898B2 (enExample)
EP (1) EP2135274A4 (enExample)
JP (1) JP2010524237A (enExample)
KR (1) KR20100014714A (enExample)
CN (1) CN101647105B (enExample)
TW (1) TWI440088B (enExample)
WO (1) WO2008124240A1 (enExample)

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US9269634B2 (en) * 2011-05-16 2016-02-23 Globalfoundries Inc. Self-aligned metal gate CMOS with metal base layer and dummy gate structure
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US9202746B2 (en) * 2013-12-31 2015-12-01 Globalfoundries Singapore Pte. Ltd. Integrated circuits with improved gap fill dielectric and methods for fabricating same
US20150206803A1 (en) * 2014-01-19 2015-07-23 United Microelectronics Corp. Method of forming inter-level dielectric layer
US9378963B2 (en) * 2014-01-21 2016-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned contact and method of forming the same
CN105097851A (zh) * 2014-05-04 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种cmos图像传感器及其制造方法和电子装置
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US9773682B1 (en) * 2016-07-05 2017-09-26 United Microelectronics Corp. Method of planarizing substrate surface
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US11549175B2 (en) 2018-05-03 2023-01-10 Lam Research Corporation Method of depositing tungsten and other metals in 3D NAND structures
WO2020123987A1 (en) 2018-12-14 2020-06-18 Lam Research Corporation Atomic layer deposition on 3d nand structures
KR20210141762A (ko) 2019-04-11 2021-11-23 램 리써치 코포레이션 고 단차 커버리지 (step coverage) 텅스텐 증착
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