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  • H01L21/3105—After-treatment
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  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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  • H01L21/3105—After-treatment
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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
  • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
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  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H01L21/76832—Multiple layers
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  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention is directed in general to the field of semiconductor devices.
• the present invention relates to the fabrication of interlayer dielectric layers used in floating gate or other semiconductor device structures. Description of the Related Art
• Semiconductor devices typically include device components (such as transistors and capacitors) that are formed on or in a substrate as part of the front end of line (FEOL) processing.
• interconnect features such as contacts, metal lines and vias
• BEOL back end of line
• the BEOL dielectric layers typically include a layer of boro-phosphorous tetra-ethyl ortho-silicate (BPTEOS) that forms all or part of the first inter-layer dielectric (ILDO), which is sometime also referred to as the pre-metal dielectric (PMD).
• BPTEOS boro-phosphorous tetra-ethyl ortho-silicate
• ILDO first inter-layer dielectric
• PMD pre-metal dielectric
• the BPTEOS layer provides a gettering function to help protect non- volatile memories (NVM) from the effects of mobile ions that can affect the data retention performance of the NVM cell(s).
• NVM non- volatile memories
• the BPTEOS layer can also help control the field leakage between semiconductor transistors, such as those formed in an array of transistors.
• FIG. 1 depicts a semiconductor device 10 in which device components (such as transistors 12, 13) are formed on or in a substrate 11.
• the depicted device components 12, 13 shown in simplified schematic form can represent any type of transistor device (such as a MOSFET, DRAM or NVM device), and may be formed using any desired transistor fabrication sequence which forms a gate electrode and a gate dielectric layer over the substrate 11 and uses a sidewall spacer on the gate electrode to form at least part of the source/drain region(s) (not shown) in the substrate 11.
• the gettering layer is formed by depositing a BPTEOS layer 14 over the device components 12, 13.
• the BPTEOS layer 14 forms more thickly at the top of the device components 12, 13 and pinches off the opening, thereby forming a void region 15 in the BPTEOS layer 14.
• the presence of voids in the ILDO layer can trap mobile ions that are generated in the course of subsequent processing steps, such as ions from chemical mechanical polish slurry materials used in subsequent polishing steps and from other processing and/or cleaning steps.
• the presence of mobile ions in the device can reduce device yield and impair performance, particularly with NVM devices.
• subsequent contact formation steps can create conductive stringers in the voids (e.g., tungsten stringers), thereby shorting two or more contacts together.
• the subsequent polishing steps can also reduce or eliminate the protective function provided by the BPTEOS layer 14. This can occur during planarization of the ILDO layer, when the BPTEOS layer 14 is part of a stack of films included in the ILDO stack and is polished off to expose at least part of the underlying semiconductor device 20, as illustrated in Figure 2.
• CMP chemical mechanical polish
• variations in the CMP polish rate can remove or thin the BPTEOS layer 14 in some areas, thereby removing the gettering protective function in those areas.
• the polish removes only part of the BPTEOS layer 14 the remaining exposed BPTEOS layer can be exposed to impurities in the atmosphere which can be trapped in the BPTEOS layer, thereby reducing its gettering efficiency.
• Figure 1 is a partial cross-sectional view of a semiconductor device on which is formed a single layer BPTEOS layer having a void;
• Figure 2 illustrates processing subsequent to Figure 1 after planarization of the BPTEOS layer
• Figure 3 is a partial cross-sectional view of a semiconductor device in which NVM device components are formed on a substrate;
• Figure 4 illustrates processing subsequent to Figure 3 after deposition of an etch stop layer
• Figure 5 illustrates processing subsequent to Figure 4 after deposition of a gap fill layer formed with one or more dielectric film layers
• Figure 6 illustrates processing subsequent to Figure 5 after the gap fill layer is planarized with a chemical mechanical polish step
• Figure 7 illustrates processing subsequent to Figure 6 after deposition of a first gettering dielectric layer
• Figure 8 illustrates processing subsequent to Figure 7 after deposition of a second dielectric layer
• Figure 9 illustrates processing subsequent to Figure 8 after a contact opening is formed to exposed one or more device components
• FIG. 10 is a flow diagram illustrating a process for forming an ILDO stack having a gettering layer with substantially uniform thickness.
• a method and apparatus are described for forming a first inter-layer dielectric (ILDO) on a semiconductor device where the ILDO layer includes a protective gettering layer having a substantially uniform thickness.
• the ILDO layer is formed by depositing an etch stop layer (e.g., plasma-enhanced silicon nitride) over the semiconductor devices to protect the underlying gate stack during subsequent contact etch process(es) and to provide some protection against mobile ions.
• an etch stop layer e.g., plasma-enhanced silicon nitride
• a more robust protection is required.
• a robust gettering protection is provided in an ILDO stack by first forming a gap fill layer over the etch stop layer to a thickness that completely covers the gates and overfills the regions between semiconductor devices so as to reduce or eliminate the formation of voids or cores.
• the gap fill layer may be formed by conformally depositing a dielectric layer of sub-atmospheric tetra-ethyl ortho silicate (SATEOS) or high density plasma (HDP) oxide, or by using any dielectric that completely fills the gaps. If the gap fill material has an undesirably high polish rate or cannot withstand CMP processing, a stable polish layer may be formed over the gap fill material using an appropriate dielectric material, such as phosphorous doped TEOS (PTEOS).
• PTEOS phosphorous doped TEOS
• a gettering layer is formed over the planarized gap fill layer or stack, such as by depositing a dielectric layer of BPTEOS, PTEOS or boron doped TEOS (BTEOS).
• BTEOS boron doped TEOS
• an additional dielectric may be formed over the gettering layer by depositing a dense dielectric layer, such as plasma enhanced TEOS (PETEOS).
• PETEOS plasma enhanced TEOS
• the additional dielectric layer acts as a cap for the gettering film to protect the gettering film against exposure to atmospheric impurities during subsequent processing.
• the dense dielectric layer also provides structural support to anchor subsequently formed metal trenches (e.g., Cu), and may also provide a copper diffusion barrier function to prevent subsequently formed copper from diffusing through the ILDO layer.
• the gap fill layer may be formed with an HDP doped dielectric film (such as HDP BPTEOS or HDP PTEOS) and an optional polish cap layer, and then polished with a CMP process so that a subsequently deposited TEOS metal anchor cap layer may be formed on a planar surface.
• HDP doped dielectric film such as HDP BPTEOS or HDP PTEOS
• polish cap layer such as HDP BPTEOS or HDP PTEOS
• CMP process polish cap layer
• one or more of the gap fill layer, gettering layer and additional dielectric layer may optionally be densified with one or more anneal process steps.
• the gettering film is formed on a planarized dielectric with good interface and has a substantially uniform thickness and that is not polished off or exposed.
• contact openings are etched to expose the underlying semiconductor device(s), and then any desired back end of line processing, such as standard CMOS BEOL processing, may be used to complete the device.
• voids in the ILDO layer are reduced or eliminated and gettering protection is enhanced, thereby increasing manufacturing yield, particularly for NVM products with aggressive contact plug aspect ratio, though the disclosed techniques can be used for any product or technology where voids in the plug limits yield.
• FIG. 3 a partial cross-sectional view is shown of a semiconductor device 30 in which transistor device components (such as MOS, NVM or DRAM devices) 32, 33 are formed on a substrate 31.
• transistor device components such as MOS, NVM or DRAM devices
• the substrate 31 may be implemented as a bulk silicon substrate, single crystalline silicon (doped or undoped), or any semiconductor material including, for example, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP as well as other Group III-IV compound semiconductors or any combination thereof, and may optionally be formed as the bulk handling wafer.
• the substrate 31 may be implemented as the top semiconductor layer of a semiconductor on-insulator (SOI) structure or a hybrid substrate comprised of bulk and/or SOI regions with differing crystal orientation.
• SOI semiconductor on-insulator
• each of the device components 32, 33 is a non-volatile memory (NVM) device having a channel region over which is formed an NVM gate stack which includes a first insulating or tunnel dielectric layer, a floating gate 34 formed over the first layer, a control dielectric layer(s) 35 (e.g., ONO layer) formed over the floating gate 34, and a control gate 36 formed over the dielectric layer 35.
• NVM non-volatile memory
• one or more sidewall spacers 37 formed on the side of the NVM gate stack 32, 33 are typically used in the formation of source and drain regions (not shown) in the substrate 31.
• the floating gates 34 are illustrated as being lifted on the edges from oxide encroachment, this is not a required feature of the present invention.
• the floating gate layer 34 acts as a charge storage layer that is charged under control of the control gate 36 and tunnel dielectric.
• any desired front end of line processing sequence may be used.
• NVM devices including floating gate devices, including nanocrystal devices and SONOS (silicon-oxide-nitride-oxide-silicon) devices.
• Figure 4 illustrates processing of a semiconductor device 40 subsequent to Figure 3 after deposition of an etch stop layer 42 which may be formed by depositing silicon nitride to serve as a first mobile ion barrier layer. Any desired material may be used to form the etch stop layer 42, so long as the material protects the underlying device components 32, 33 from etch and/or ash damage when the contact holes are opened.
• etch stop layer 42 may be formed by depositing silicon nitride to serve as a first mobile ion barrier layer. Any desired material may be used to form the etch stop layer 42, so long as the material protects the underlying device components 32, 33 from etch and/or ash damage when the contact holes are opened.
• the etch stop layer 42 may be formed by depositing a layer of plasma- enhanced silicon nitride (SiN) or silicon carbonitride (SiCN) using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.
• CVD chemical vapor deposition
• PECVD plasma-enhanced chemical vapor deposition
• PVD physical vapor deposition
• ALD atomic layer deposition
• the etch stop layer 42 is formed by depositing plasma-enhanced silicon nitride to a thickness of approximately 20-50 nanometers, though other thicknesses may also be used.
• the etch stop layer 42 protects the underlying devices 32, 33 during subsequent contact etch process(es) and also provides protection against mobile ions, to the extent that silicon nitride acts as a barrier to mobile ions. However, to the extent that mobile ions are able to penetrate the silicon nitride etch stop layer at the seam lines 44, the silicon nitride layer 42 provides only part of the gettering protection function for the devices 32, 33.
• Figure 5 illustrates processing of a semiconductor device 50 subsequent to Figure 4 after deposition of a gap fill layer 52 over the etch stop layer 42.
• the deposited gap fill layer 52 forms at least part of a first interlayer dielectric stack that electrically isolates the device components 32, 33 formed on the substrate 31 from one another.
• the first interlayer dielectric stack ILDO
• the first interlayer dielectric stack is formed with one or more dielectric pre -metal inter-level dielectric layers, including a gap fill layer 52 formed over the device components 32, 33 to a thickness of approximately 500-10000 Angstroms, though other thicknesses may also be used.
• the gap fill layer 52 is formed by depositing a conformal layer of silicon dioxide or other dielectric material using CVD, PECVD, PVD, ALD or any combination thereof.
• the material used to form the gap fill layer 52 is chosen to completely fill in the high aspect ratio regions between device components 32, 33 (such as are present particularly with NVM arrays) so that voids and metal stringer shorts (described above) are not formed.
• the deposited gap fill layer 52 can be planarized to form an ILDO base layer on which one or more gettering dielectric layers (e.g., a BPTEOS layer) may be formed, as described hereinbelow.
• the gap fill layer 52 is formed by depositing sub-atmospheric tetra-ethyl ortho-silicate (SATEOS) to a thickness of at least approximately 1000-4000 Angstroms, which is sufficient to fill in the regions between device components, though other thicknesses may also be used.
• SATEOS sub-atmospheric tetra-ethyl ortho-silicate
• the gap fill layer 52 may be formed with low-pressure TEOS (LPTEOS) CVD, plasma-enhanced TEOS (PETEOS), CVD and/or SiO x N y , atmospheric pressure TEOS (APTEOS) CVD, HDP BPTEOS or HDP plasma enhanced PTEOS.
• LPTEOS low-pressure TEOS
• PETEOS plasma-enhanced TEOS
• APTEOS atmospheric pressure TEOS
• HDP BPTEOS high pressure TEOS
• HDP plasma enhanced PTEOS high pressure TEOS
• a stable polish layer may be formed over the gap fill 52 using an appropriate dielectric material, such as PETEOS.
• the gap fill layer 52 forms an ILDO base layer that substantially fills in the regions between devices components 32, 33, thereby reducing or eliminating the formation of voids or cores.
• the gap fill layer 52 is deposited to a sufficient thickness that a subsequent polish step will create a substantially planar surface on which a gettering layer of BPTEOS, BTEOS and/or PTEOS material may be formed.
• Figure 6 illustrates processing of a semiconductor device 60 subsequent to Figure 5 after the gap fill layer 52 is planarized. While any desired planarization process may be used, in accordance with various embodiments, the gap fill layer 52 is planarized with an ILDO planarization process that uses a chemical mechanical polish step to form a substantially planar surface 62 on the gap fill layer 52. By using a timed CMP process, the material from the upper region of the gap fill layer 52 is removed without also removing or exposing the etch stop layer 42.
• Figure 7 illustrates processing of a semiconductor device 70 subsequent to
• the gettering dielectric layer 72 may be formed by depositing a layer of BPTEOS, PTEOS, BTEOS or a combination thereof using CVD, PECVD, PVD, ALD or any combination thereof.
• the gettering dielectric layer 72 is formed by depositing BPTEOS to a thickness of approximately 10-100 nanometers, and more preferably 20-50 nanometers, though other thicknesses may also be used.
• the gettering dielectric layer 72 effectively acts as a getter to mobile ions which can affect the performance of devices, such as NVM memories.
• the gettering dielectric layer 72 may be densified with one or more anneal process steps, though it will be appreciated that an anneal process may also be applied subsequently in the fabrication process.
• the gettering dielectric layer 72 protects the underlying devices 32, 33 against mobile ions.
• the gettering film layer 72 is formed as a continuous layer that is more effective in gettering mobile ions.
• the interface between the gap fill material and the gettering material is improved.
• the disclosed methodology produces an intact and continuous layer of gettering material.
• FIG 8 illustrates processing of a semiconductor device 80 subsequent to Figure 7 after deposition of a second or capping dielectric layer 82. While any desired material may be used to form the capping dielectric layer 82, various embodiments of the present invention form the capping dielectric layer 82 by depositing a layer of TEOS using CVD, PECVD, PVD, ALD or any combination thereof. In a selected embodiment, the additional capping dielectric layer 82 is formed by depositing PETEOS to a thickness of approximately 500-5000 Angstroms, and more preferably 1000 Angstroms, though other thicknesses may also be used.
• the additional dielectric layer 82 When formed with a dense dielectric layer, such as TEOS, the additional dielectric layer 82 provides structural support to anchor subsequently formed metal contact regions, and may also provide a copper diffusion barrier function to prevent subsequently formed copper from diffusing through the lower ILDO layer(s). In addition, this TEOS cap protects the gettering film from exposure to the atmosphere where it can be exposed to other impurities which could reduce its efficiency as a gettering material.
• a dense dielectric layer such as TEOS
• FIG 9 illustrates processing of a semiconductor device 90 subsequent to Figure 8 after one or more contact openings 92, 94, 96 are formed to exposed one or more device components.
• each contact opening 92, 94, 96 is etched through the ILDO stack to expose the etch stop layer 42 over an intended contact region of an underlying device component, such as a source/drain region (not shown) formed in a substrate 31 or a gate electrode on the device component 32, 33.
• the contact opening 94 over the source/drain region has a width of approximately 500-3000 Angstroms, more preferably less than approximately 2000 Angstroms.
• the result aspect ratio (heightwidth) for such devices is greater than about 1.5 to more than 4:1, though aspect ratios in future generation process technologies will be still higher.
• Any desired photolithography and/or selective etch techniques can be used to form the contact opening 92, 94, 96.
• the contact opening 94 may be formed by depositing and patterning a protective mask or photoresist layer over the gettering dielectric layer 72 and/or additional dielectric layer 82 in which a contact hole is defined (not shown), and then anisotropic etching (e.g., reactive ion etching) the exposed ILDO stack to form the contact opening 94.
• anisotropic etching e.g., reactive ion etching
• a three stage etch process is used which removes selected portions of the second dielectric layer 82, the gettering layer 72, and the gap fill layer 52 before reaching the etch stop layer 42 formed over a selected contact region (and/or gate electrode).
• a layer of photoresist may be applied and patterned directly on the second dielectric layer 82, though multi-layer masking techniques may also be used to define the locations of the contact openings 92, 94, 96.
• the exposed portions of the second dielectric layer 82, gettering dielectric layer 72 and gap fill layer 52 are then removed by using the appropriate etchant processes to etch the contact openings 92, 94, 96, such as an anisotropic reactive ion etching (RIE) process using O 2 , N 2 , or a fluorine-containing gas.
• RIE anisotropic reactive ion etching
• one or more etch processes that are selective for the dielectric materials in the ILDO stack layers 82, 72, 52 are used to etch through to the exposed portion of the etch stop layer 42.
• One or more additional etch and/or ash processes may be used to remove any remaining layers.
• the single PTEOS layer is formed by depositing a conformal layer of phosphorus doped TEOS using CVD, PECVD, PVD, ALD or any combination thereof. Because of the relative density of such a PTEOS layer, it can provide both the gettering and anchoring functions to anchor subsequently formed metal contacts. [029] As will be appreciated, additional processing steps may be used to complete the fabrication of the semiconductor device 90 into a functioning NVM device.
• additional backend processing steps may be performed, such as forming contact plugs and multiple levels of interconnect(s) that are used to connect the device components in a desired manner to achieve the desired functionality.
• the specific sequence of steps used to complete the fabrication of the device components may vary, depending on the process and/or design requirements.
• FIG 10 is a flow diagram illustrating an example process 100 for forming an ILDO stack having a gettering layer with substantially uniform thickness.
• the process picks up after the front end of line (FEOL) process and begins by forming an etch stop layer (step 101), such as by depositing a plasma enhanced nitride etch stop layer (PEN ESL).
• a ILDO stack is formed by depositing a gap fill dielectric layer (such as SATEOS, HDP PTEOS, etc.) at step 102.
• a CMP cap layer may also be deposited.
• the gap fill dielectric layer is planarized (e.g., with a CMP process) at step 103, a gettering layer (such as BPTEOS) is deposited at step 104, and a barrier dielectric layer (such as PETEOS) is deposited at step 105.
• a gettering layer such as BPTEOS
• a barrier dielectric layer such as PETEOS
• the barrier dielectric deposition step may be skipped.
• the first inter-layer dielectric stack is formed by first forming an etch stop layer (e.g., with deposited plasma-enhanced nitride) over a plurality of device components, such as NVM transistor devices, that are formed on a semiconductor structure. Subsequently, a dielectric gap fill layer is formed over the etch stop layer (such as by depositing a SATEOS or HDP PTEOS layer) to fill in regions between the device components. The dielectric gap file layer is then planarized (e.g., with a CMP process) down to a substantially planar surface.
• an etch stop layer e.g., with deposited plasma-enhanced nitride
• a dielectric gap fill layer is formed over the etch stop layer (such as by depositing a SATEOS or HDP PTEOS layer) to fill in regions between the device components.
• the dielectric gap file layer is then planarized (e.g., with a CMP process) down to a substantially planar surface.
• a stable polish cap layer may be formed over the dielectric gap fill layer such that the stable polish cap layer and dielectric gap fill layer are planarized while planarizing the dielectric gap fill layer.
• a dielectric gettering layer is formed, such as by depositing a BPTEOS, BTEOS or PTEOS layer or combination thereof.
• a dielectric capping layer e.g., PETEOS
• PETEOS PETEOS
• the dielectric gettering layer and the dielectric gap fill layer are selectively etched to expose the etch stop layer over one or more contact regions in one or more device components, and then the exposed etch stop layer is selectively etched to expose the contact regions.
• a method and system for manufacturing a semiconductor device on which are formed a plurality of device components is formed by depositing a dielectric layer over the plurality of device components to fill in regions between the plurality of device components.
• an etch stop layer may be formed over the plurality of device components prior to forming the gap fill layer.
• the gap fill layer may be formed in part by depositing a SATEOS or HDP doped TEOS layer over the plurality of device components to fill in regions between the plurality of device components, and may also include a deposited stable polish cap layer over the dielectric layer.
• a gettering layer is deposited over the substantially planar surface of the gap fill layer.
• the gettering layer may be formed in part by depositing a BPTEOS layer, PTEOS layer or BTEOS layer or a combination thereof over the substantially planar surface of the gap fill layer.
• the gettering layer may be formed by depositing one or more doped TEOS layers over the substantially planar surface of the gap fill layer, and then depositing an anchor layer formed from TEOS or plasma enhanced TEOS over the one or more doped TEOS layers.
• the gettering layer and the gap fill layer dielectric layer may be selectively etched to expose one or more contact regions in one or more device components.
• a method and system for forming a first inter-layer dielectric stack by first forming a planarized gap fill layer over a plurality of device components to cover the plurality of device components and to fill in regions between the plurality of device components.
• the planarized gap fill layer may be formed by depositing a SATEOS or HDP doped TEOS layer over the plurality of device components to fill in regions between the plurality of device components, and then polishing the SATEOS or HDP doped TEOS layer down to a substantially planar surface.
• one or more gettering layers are deposited so that an opening can be selectively etched in the one or more gettering layers and planarized gap fill layer to expose one or more contact regions in one or more device components.
• the gettering layers are formed by depositing one or more doped TEOS layers over the planarized gap fill layer, and then depositing an anchor layer formed from TEOS or plasma enhanced TEOS over the one or more doped TEOS layers.
• the methodology of the present invention may be applied using materials other than expressly set forth herein.
• the invention is not limited to any particular type of integrated circuit described herein. Accordingly, the foregoing description is not intended to limit the invention to the particular form set forth, but on the contrary, is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims so that those skilled in the art should understand that they can make various changes, substitutions and alterations without departing from the spirit and scope of the invention in its broadest form.

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