KR20100014714A - 비휘발성 메모리를 위한 제1 층간 유전체 스택 - Google Patents

비휘발성 메모리를 위한 제1 층간 유전체 스택 Download PDF

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Publication number
KR20100014714A
KR20100014714A KR1020097020504A KR20097020504A KR20100014714A KR 20100014714 A KR20100014714 A KR 20100014714A KR 1020097020504 A KR1020097020504 A KR 1020097020504A KR 20097020504 A KR20097020504 A KR 20097020504A KR 20100014714 A KR20100014714 A KR 20100014714A
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layer
dielectric
gap fill
forming
device components
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올루분미 오. 아데투투
크리스토퍼 비. 헌들레이
폴 에이. 인거솔
크랙 티. 스위프트
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프리스케일 세미컨덕터, 인크.
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020097020504A 2007-04-05 2008-03-12 비휘발성 메모리를 위한 제1 층간 유전체 스택 Withdrawn KR20100014714A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/697,106 US8435898B2 (en) 2007-04-05 2007-04-05 First inter-layer dielectric stack for non-volatile memory
US11/697,106 2007-04-05

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KR20100014714A true KR20100014714A (ko) 2010-02-10

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Country Link
US (1) US8435898B2 (enExample)
EP (1) EP2135274A4 (enExample)
JP (1) JP2010524237A (enExample)
KR (1) KR20100014714A (enExample)
CN (1) CN101647105B (enExample)
TW (1) TWI440088B (enExample)
WO (1) WO2008124240A1 (enExample)

Cited By (8)

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KR20140123456A (ko) * 2013-04-12 2014-10-22 램 리써치 코포레이션 고 체적 제조 애플리케이션들을 위한 ｃｖｄ 기반 금속/반도체 오믹 컨택트
US11348795B2 (en) 2017-08-14 2022-05-31 Lam Research Corporation Metal fill process for three-dimensional vertical NAND wordline
US11549175B2 (en) 2018-05-03 2023-01-10 Lam Research Corporation Method of depositing tungsten and other metals in 3D NAND structures
US11972952B2 (en) 2018-12-14 2024-04-30 Lam Research Corporation Atomic layer deposition on 3D NAND structures
US12002679B2 (en) 2019-04-11 2024-06-04 Lam Research Corporation High step coverage tungsten deposition
US12077858B2 (en) 2019-08-12 2024-09-03 Lam Research Corporation Tungsten deposition
US12237221B2 (en) 2019-05-22 2025-02-25 Lam Research Corporation Nucleation-free tungsten deposition
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition

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US8895441B2 (en) * 2012-02-24 2014-11-25 Lam Research Corporation Methods and materials for anchoring gapfill metals
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US9202746B2 (en) * 2013-12-31 2015-12-01 Globalfoundries Singapore Pte. Ltd. Integrated circuits with improved gap fill dielectric and methods for fabricating same
US20150206803A1 (en) * 2014-01-19 2015-07-23 United Microelectronics Corp. Method of forming inter-level dielectric layer
US9378963B2 (en) * 2014-01-21 2016-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned contact and method of forming the same
CN105097851A (zh) * 2014-05-04 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种cmos图像传感器及其制造方法和电子装置
US9378968B2 (en) * 2014-09-02 2016-06-28 United Microelectronics Corporation Method for planarizing semiconductor device
CN106684041B (zh) * 2015-11-10 2020-12-08 联华电子股份有限公司 半导体元件及其制作方法
US9773682B1 (en) 2016-07-05 2017-09-26 United Microelectronics Corp. Method of planarizing substrate surface
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
KR20140123456A (ko) * 2013-04-12 2014-10-22 램 리써치 코포레이션 고 체적 제조 애플리케이션들을 위한 ｃｖｄ 기반 금속/반도체 오믹 컨택트
US11348795B2 (en) 2017-08-14 2022-05-31 Lam Research Corporation Metal fill process for three-dimensional vertical NAND wordline
US11549175B2 (en) 2018-05-03 2023-01-10 Lam Research Corporation Method of depositing tungsten and other metals in 3D NAND structures
US11972952B2 (en) 2018-12-14 2024-04-30 Lam Research Corporation Atomic layer deposition on 3D NAND structures
US12002679B2 (en) 2019-04-11 2024-06-04 Lam Research Corporation High step coverage tungsten deposition
US12237221B2 (en) 2019-05-22 2025-02-25 Lam Research Corporation Nucleation-free tungsten deposition
US12077858B2 (en) 2019-08-12 2024-09-03 Lam Research Corporation Tungsten deposition

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Publication number Publication date
CN101647105A (zh) 2010-02-10
US20080248649A1 (en) 2008-10-09
TW200849386A (en) 2008-12-16
EP2135274A4 (en) 2011-07-27
CN101647105B (zh) 2012-07-04
WO2008124240A1 (en) 2008-10-16
TWI440088B (zh) 2014-06-01
US8435898B2 (en) 2013-05-07
JP2010524237A (ja) 2010-07-15
EP2135274A1 (en) 2009-12-23

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