JP2010524237A5 - - Google Patents
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- JP2010524237A5 JP2010524237A5 JP2010502176A JP2010502176A JP2010524237A5 JP 2010524237 A5 JP2010524237 A5 JP 2010524237A5 JP 2010502176 A JP2010502176 A JP 2010502176A JP 2010502176 A JP2010502176 A JP 2010502176A JP 2010524237 A5 JP2010524237 A5 JP 2010524237A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- dielectric
- gap filling
- forming
- dielectric gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Claims (6)
- 半導体構造上に第1層間誘電体を形成するための方法において、
前記半導体構造上に複数のデバイス部品を形成するデバイス部品形成工程と、
前記複数のデバイス部品の上方にエッチング停止層を形成するエッチング停止層形成工程と、
前記複数のデバイス部品の間の領域を充填するために、前記エッチング停止層の上方に誘電体間隙充填層を形成する誘電体間隙充填層形成工程と、
前記誘電体間隙充填層を略平坦面になるまで平坦化する平坦化工程と、
前記誘電体間隙充填層の略平坦面の上方に誘電体ゲッタリング層を形成する誘電体ゲッタリング層形成工程と、
一つまたは複数のデバイス部品内の一つまたは複数のコンタクト領域の上方で前記エッチング停止層を露出させるために、前記誘電体ゲッタリング層と前記誘電体間隙充填層とを選択的にエッチングするエッチング工程と
を備える方法。 - 前記誘電体間隙充填層形成工程は、前記複数のデバイス部品の間の領域を充填するために、SATEOS層またはHDP PTEOS層を堆積する工程を備える、請求項1に記載の方法。
- 前記誘電体間隙充填層形成工程は、前記誘電体間隙充填層を略平坦な面に平坦化するために、化学的機械的研磨工程を使用する工程を備える、請求項1に記載の方法。
- 前記誘電体ゲッタリング層形成工程は、可動イオンバリア層を設けるために、誘電体間隙充填層の略平坦面の上方にBPTEOS層、PTEOS層、BTEOS層、またはそれらを組み合わせたものを堆積する工程を含む、請求項1に記載の方法。
- 前記誘電体ゲッタリング層を選択的にエッチングする前に、前記誘電体ゲッタリング層の上方に誘電体キャッピング層を形成する誘電体キャッピング層形成工程をさらに備える、請求項1に記載の方法。
- 前記誘電体間隙充填層を平坦化するときに安定研磨キャップ層と誘電体間隙充填層とが平坦化されるように、前記誘電体間隙充填層の上方に安定研磨キャップ層を形成する安定研磨キャップ層形成工程をさらに備える、請求項1に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/697,106 US8435898B2 (en) | 2007-04-05 | 2007-04-05 | First inter-layer dielectric stack for non-volatile memory |
PCT/US2008/056562 WO2008124240A1 (en) | 2007-04-05 | 2008-03-12 | A first inter-layer dielectric stack for non-volatile memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010524237A JP2010524237A (ja) | 2010-07-15 |
JP2010524237A5 true JP2010524237A5 (ja) | 2011-04-21 |
Family
ID=39827325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010502176A Pending JP2010524237A (ja) | 2007-04-05 | 2008-03-12 | 不揮発性メモリの第1層間誘電体スタック |
Country Status (7)
Country | Link |
---|---|
US (1) | US8435898B2 (ja) |
EP (1) | EP2135274A4 (ja) |
JP (1) | JP2010524237A (ja) |
KR (1) | KR20100014714A (ja) |
CN (1) | CN101647105B (ja) |
TW (1) | TWI440088B (ja) |
WO (1) | WO2008124240A1 (ja) |
Families Citing this family (21)
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EP2617771B1 (de) * | 2010-01-14 | 2016-04-06 | Basf Se | Verfahren zur Herstellung von expandierbaren Polymilchsäure-haltigen Granulaten |
US9269634B2 (en) * | 2011-05-16 | 2016-02-23 | Globalfoundries Inc. | Self-aligned metal gate CMOS with metal base layer and dummy gate structure |
US8519482B2 (en) * | 2011-09-28 | 2013-08-27 | Globalfoundries Singapore Pte. Ltd. | Reliable contacts |
US8895441B2 (en) * | 2012-02-24 | 2014-11-25 | Lam Research Corporation | Methods and materials for anchoring gapfill metals |
US9153486B2 (en) * | 2013-04-12 | 2015-10-06 | Lam Research Corporation | CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications |
EP2884666B1 (en) * | 2013-12-10 | 2019-01-02 | IMEC vzw | FPGA device with programmable interconnect in back end of line portion of the device. |
KR102125749B1 (ko) | 2013-12-27 | 2020-07-09 | 삼성전자 주식회사 | 반도체 장치 및 이의 제조 방법 |
US9202746B2 (en) * | 2013-12-31 | 2015-12-01 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with improved gap fill dielectric and methods for fabricating same |
US20150206803A1 (en) * | 2014-01-19 | 2015-07-23 | United Microelectronics Corp. | Method of forming inter-level dielectric layer |
US9378963B2 (en) * | 2014-01-21 | 2016-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned contact and method of forming the same |
CN105097851A (zh) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 一种cmos图像传感器及其制造方法和电子装置 |
US9378968B2 (en) * | 2014-09-02 | 2016-06-28 | United Microelectronics Corporation | Method for planarizing semiconductor device |
CN106684041B (zh) * | 2015-11-10 | 2020-12-08 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
US9773682B1 (en) | 2016-07-05 | 2017-09-26 | United Microelectronics Corp. | Method of planarizing substrate surface |
KR20200032756A (ko) | 2017-08-14 | 2020-03-26 | 램 리써치 코포레이션 | 3차원 수직 nand 워드라인을 위한 금속 충진 프로세스 |
US11549175B2 (en) | 2018-05-03 | 2023-01-10 | Lam Research Corporation | Method of depositing tungsten and other metals in 3D NAND structures |
US11972952B2 (en) | 2018-12-14 | 2024-04-30 | Lam Research Corporation | Atomic layer deposition on 3D NAND structures |
KR20210141762A (ko) | 2019-04-11 | 2021-11-23 | 램 리써치 코포레이션 | 고 단차 커버리지 (step coverage) 텅스텐 증착 |
CN111490005A (zh) * | 2020-05-26 | 2020-08-04 | 上海华虹宏力半导体制造有限公司 | 间隙填充方法、闪存的制作方法及半导体结构 |
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-
2007
- 2007-04-05 US US11/697,106 patent/US8435898B2/en active Active
-
2008
- 2008-03-12 JP JP2010502176A patent/JP2010524237A/ja active Pending
- 2008-03-12 CN CN200880010706.9A patent/CN101647105B/zh active Active
- 2008-03-12 WO PCT/US2008/056562 patent/WO2008124240A1/en active Application Filing
- 2008-03-12 KR KR1020097020504A patent/KR20100014714A/ko not_active Application Discontinuation
- 2008-03-12 EP EP08731927A patent/EP2135274A4/en not_active Withdrawn
- 2008-04-03 TW TW097112428A patent/TWI440088B/zh active
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