CN202930362U - 一种半导体器件 - Google Patents

一种半导体器件 Download PDF

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CN202930362U
CN202930362U CN2010900007966U CN201090000796U CN202930362U CN 202930362 U CN202930362 U CN 202930362U CN 2010900007966 U CN2010900007966 U CN 2010900007966U CN 201090000796 U CN201090000796 U CN 201090000796U CN 202930362 U CN202930362 U CN 202930362U
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尹海洲
朱慧珑
骆志炯
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Abstract

一种具有双接触孔的半导体器件及其制造方法，该方法包括：在半导体衬底(200)上形成源极/漏极区域(210)和替代栅结构；沉积第一层间介电层(280)；对第一层间介电层进行平坦化处理，以暴露出替代栅结构中的替代栅；去除替代栅，并沉积形成金属栅(220)；在第一层间介电层中形成第一源/漏区接触孔(240)；在第一层间介电层上沉积第二层间介电层(380)；在第二层间介电层中形成第二源/漏区接触孔(340)和栅区接触孔(330)。

Description

一种半导体器件
技术领域
本实用新型涉及半导体领域，尤其涉及半导体器件及其制造方法，更具体地，涉及一种用于替代栅的双接触孔形成方法以及利用所述方法制造出的半导体器件。 
背景技术
随着半导体器件的尺寸越来越小，层间触点和接触孔(CA)也越来越小，且相互间的距离也随之减小。利用传统工艺制造较小的触点和接触孔存在以下一些问题：(1)由于栅上的刻蚀深度与源/漏区中的刻蚀深度不同，容易造成接触孔与栅之间的短路；(2)由于源/漏区中的刻蚀深度较深且开口较小(即，具有较小的宽高比)，可能会引起无法完全刻通、插头填充金属中出现空洞等多种工艺缺陷，从而限制了工艺的选择性，而且导致了寄生电阻的增大。 
以下，将结合图1，对传统工艺所引起的问题进行详细描述。图1是示出了根据传统工艺制造的半导体器件的示意图。如图1所示，根据传统工艺制造的半导体器件主要包括：Si衬底100、层间介电层180、硅化物区域110、金属栅120、源/漏区接触孔140和栅区接触孔130，其中金属栅120形成在高k介电层170上，高k介电层170沉积在Si衬底100上，在高k介电层170和金属栅120周围形成有侧壁160；层间介电层180沉积在Si衬底100上；硅化物区域110形成在Si衬底100上，嵌入在Si衬底100中；源/漏区接触孔140和栅区接触孔130形成在层间介电层180中，源/漏区接触孔140分别与硅化物区域110相接触，栅区接触孔130与金属栅120相接触。源/漏区接触孔140和栅区接触孔130分别包括衬里125和填充在其中的导电金属。如图1所示，为了形成栅区接触孔130而执行的刻蚀工艺的刻蚀深度Hca_gate与为了形成源/漏区接触孔140而执行的刻蚀工艺的刻蚀深度Hca_sd不同，源/漏区接触孔140具有更小的宽高比，因此在源/漏区接触孔140的形成过程中，更容易产生无法完全刻通、插头填充金属中出现空洞等多种工艺缺陷。 
而且，由于源/漏区接触孔140的刻蚀工艺要求较高，极有可能导致源/漏区接触孔140与金属栅120之间的短路(图1中的虚线所示)。 
实用新型内容
考虑到传统工艺的上述缺陷，本实用新型提出了一种用于替代栅的双接触孔形成方法，从而在源/漏区和栅区上形成具有相同刻蚀深度的源/漏区接触孔和栅区接触孔，在避免了源/漏区接触孔与栅之间的短路的同时，防止了工艺缺陷的形成；此外，本实用新型与替代栅工艺兼容。 
根据本实用新型的一个方面，提出了一种半导体器件，其特征在于，所述半导体器件包括：半导体衬底，具有形成在其上的源极/漏极区域和栅结构，所述栅结构包括金属栅；第一层间介电层，沉积在所述半导体衬底上，具有形成在其中的第一源/漏区接触孔，所述第一源/漏区接触孔与所述源极/漏极区域相接触；以及第二层间介电层，沉积在所述第一层间介电层上，具有形成在其中的第二源/漏区接触孔和栅区接触孔，所述第二源/漏区接触孔与所述第一源/漏区接触孔相接触，以及所述栅区接触孔与所述金属栅相接触，所述第一源/漏区接触孔、所述第二源/漏区接触孔和所述栅区接触孔分别包括衬里和填充在其中的导电金属，所述衬里由从以下材料组中选择的至少一种材料构成：TiN、TaN、Ta和Ti，以及所述导电金属由从以下材料组中选择的至少一种材料构成：Ti、Al、TiAl、Cu和W；其中所述第二源/漏区接触孔与所述栅区接触孔具有相同的深度。 
根据本实用新型的实施例，所述第一源/漏区接触孔的宽度为15～100nm，所述第二源/漏区接触孔的宽度为20～150nm，以及所述栅区接触孔的宽度为20～150nm。 
根据本实用新型的实施例，所述半导体器件还包括：阻挡衬里，形成在所述第一层间介电层和所述半导体衬底之间。 
根据本实用新型的实施例，所述阻挡衬里由Si3N4构成，且厚度为10～50nm。 
根据本实用新型的实施例，所述半导体器件还包括：阻挡层，形成在所述第一层间介电层和所述第二层间介电层之间。 
根据本实用新型的实施例，所述阻挡层由Si3N4构成，且厚度为10～50nm。 
根据本实用新型的实施例，所述第一层间介电层的厚度为15～50nm，以及所述第二层间介电层的厚度为25～90nm。 
根据本实用新型，第二源/漏区接触孔和栅区接触孔具有相同的刻蚀深度，因而，能够有效地降低接触孔与栅之间发生短路的可能性，而且刻蚀宽高比较为接近，因而，降低了对刻蚀工艺和接触孔填充的要求，同时，也减小了发生工艺缺陷的可能性。此外，本实用新型利用替代栅工艺，与典型的替代栅流程兼容。 
附图说明
通过下面结合附图说明本实用新型的优选实施例，将使本实用新型的上述及其它目的、特征和优点更加清楚，其中： 
图1是示出了根据传统工艺制造的半导体器件的示意图；以及 
图2～14是示出了本实用新型所提出的半导体器件制造方法的各个步骤的示意图，其中图14示出了根据本实用新型所提出的半导体器件制造方法制造完成的半导体器件。 
应当注意的是，本说明书附图并非按照比例绘制，而仅为示意性的目的，因此，不应被理解为对本实用新型范围的任何限制和约束。在附图中，相似的组成部分以相似的附图标号标识。 
具体实施方式
下面参照附图对本实用新型的优选实施例进行详细说明，在描述过程中省略了对于本实用新型来说是不必要的细节和功能，以防止对本实用新型的理解造成混淆。 
首先，参考图14，对根据本实用新型所提出的工艺制造的半导体器件进行详细描述。图14是示出了根据本实用新型所提出的半导体器件制造方 法制造完成的半导体器件的示意图。 
如图14所示，根据本实用新型所提出的工艺制造的半导体器件主要包括：Si衬底200、第一层间介电层280(厚度为15～50nm)、第二层间介电层380(厚度为25～90nm)、硅化物区域210、金属栅220、第一源/漏区接触孔240(宽度为15～100nm)、第二源/漏区接触孔340(宽度为20～150nm)和栅区接触孔330(宽度为20～150nm)，其中金属栅220形成在高k介电层270(厚度为1～3nm)上，高k介电层270沉积在Si衬底200上，在高k介电层270和金属栅220周围形成有SiN侧壁260(宽度为10～40nm)；第一层间介电层280沉积在Si衬底200上；第二层间介电层380沉积在第一层间介电层280上；硅化物区域210形成在Si衬底200上，嵌入在Si衬底200中；第一源/漏区接触孔240形成在第一层间介电层280中，且分别与硅化物区域210相接触；第二源/漏区接触孔340和栅区接触孔330形成在第二层间介电层380中，第二源/漏区接触孔340分别与第一源/漏区接触孔240相接触，栅区接触孔330与金属栅220相接触。第一源/漏区接触孔240分别包括衬里225(厚度为2～15nm)和填充在其中的导电金属，以及第二源/漏区接触孔340和栅区接触孔330分别包括衬里325(厚度为2～15nm)和填充在其中的导电金属。 
根据本实用新型，第二源/漏区接触孔340和栅区接触孔330具有相同的刻蚀深度，因而，能够有效地降低接触孔与栅之间发生短路的可能性，而且刻蚀宽高比较为接近，因而，降低了对刻蚀工艺和接触孔填充的要求，同时，也减小了发生工艺缺陷的可能性。 
接下来，将结合图2～14，对根据本实用新型的半导体器件制造方法的各个步骤进行详细描述。 
首先，如图2所示，在Si衬底200上形成硅化物区域210和替代栅结构(高k介电层270、多晶硅栅320、围绕和覆盖高k介电层270和多晶硅栅320的SiN侧壁260和SiN盖层)。作为本实用新型的示例，高k介电层270的厚度为1～3nm，多晶硅栅320的厚度为20～70nm，SiN侧壁260在图示水平方向上的宽度为10～40nm，SiN盖层的厚度为15～40nm。这一步骤同样是传统工艺的一部分，这里形成了多晶硅栅320以作为替代金属栅 的替代栅。 
在形成了图2所示的结构之后，执行图3所示的步骤之前，可以在图2所示的结构上整体形成一阻挡衬里(例如，可由Si3N4构成)(未示出)，阻挡衬里的厚度为10～50nm。 
然后，如图3所示，在已形成硅化物区域210和替代栅结构的Si衬底200上沉积第一层间介电层(Inter Layer Dielectric layer)280。例如，未掺杂的氧化硅(SiO2)、各种掺杂的氧化硅(如硼硅玻璃、硼磷硅玻璃等)和氮化硅(Si3N4)等可以作为第一层间介电层280的构成材料。 
接下来，如图4所示，对第一层间介电层280进行化学机械平坦化(CMP)处理，从而暴露出替代栅结构的SiN盖层。 
然后，如图5所示，执行另外的CMP处理或针对S iN的反应离子刻蚀(RIE)处理，去除SiN盖层，暴露出替代栅结构的多晶硅栅320。 
之后，如图6所示，采用湿法刻蚀或干法刻蚀，去除多晶硅栅320。 
接下来，如图7所示，采用典型的替代栅工艺，沉积形成金属栅220。在完成这一步骤之后，作为替代栅的多晶硅栅320已经完全被金属栅220所取代。 
然后，如图8和9所示，采用光刻工艺，形成光刻胶掩模(图8)，并执行光刻、去胶工艺，在第一层间介电层280中的预定位置，形成接触孔开口，在接触孔开口的底部，暴露出位于Si衬底200上的硅化物区域210(图9)。在包含阻挡衬里(未示出)的情况下，需要刻蚀穿透位于接触孔开口的底部、硅化物区域210上的阻挡衬里，以暴露出硅化物区域210。 
之后，如图10所示，在接触孔开口中沉积形成金属插头，从而形成第一源/漏区接触孔240，使得第一源/漏区接触孔240分别与其下方相应位置的硅化物区域210相接触。在这一步骤中，首先沉积衬里225(例如， TiN、TaN、Ta或Ti，典型地，厚度在大约2nm到大约15nm之间)，然后再沉积导电金属(例如，Ti、Al、TiAl、Cu、W等)，最后再执行金属的CMP工艺。第一源/漏区接触孔240的形成工艺与传统工艺相同或类似。根据本实用新型，第一源/漏区接触孔240的宽度(图示水平宽度)为15～100nm。 
在形成了图10所示的结构之后，执行图11所示的步骤之前，可以在图10所示的结构上整体形成一阻挡层(例如，可由Si3N4构成)(未示出)，阻挡层的厚度为10～50nm。 
接下来，如图11所示，在已形成第一源/漏区接触孔240和金属栅220的第一层间介电层280上沉积第二层间介电层380。例如，未掺杂的氧化硅(SiO2)、各种掺杂的氧化硅(如硼硅玻璃、硼磷硅玻璃等)和氮化硅(Si3N4)等可以作为第二层间介电层380的构成材料。由于之前(图10)中所执行的CMP工艺，第二层间介电层380具有平坦的上表面。 
然后，如图12和13所示，采用光刻工艺，形成光刻胶掩模(图12)，并执行光刻、去胶工艺，在第二层间介电层380中的预定位置，形成接触孔开口，在接触孔开口的底部，暴露出位于第一层间介电层280中的第一源/漏区接触孔240和金属栅220(图13)。在包含阻挡层(未示出)的情况下，需要刻蚀穿透位于接触孔开口的底部、第一源/漏区接触孔240和金属栅220上的阻挡衬里，以暴露出第一源/漏区接触孔240和金属栅220。 
最后，如图14所示，在接触孔开口中沉积形成金属插头，从而形成第二源/漏区接触孔340和栅区接触孔330，使得第二源/漏区接触孔340分别与其下方相应位置的第一源/漏区接触孔240相接触，以及使得栅区接触孔330与金属栅220相接触。在这一步骤中，首先沉积衬里325(例如，TiN、TaN、Ta或Ti，典型地，厚度在大约2nm到大约15nm之间)，然后再沉积导电金属(例如，Ti、Al、TiAl、Cu、W等)，最后再执行金属的CMP工艺。第二源/漏区接触孔340和栅区接触孔330的形成工艺与传统工艺相同或类似。根据本实用新型，第二源/漏区接触孔340的宽度(图示水平宽度)为20～150nm；栅区接触孔330的宽度(图示水平宽度)为20～150nm。 
此外，根据本实用新型，可以对导电金属进行选择，从而使填充在第二源/漏区接触孔340和栅区接触孔330中的导电金属具有比填充在第一源/漏区接触孔240中的导电金属小的电阻率。例如，填充在第二源/漏区接触孔340和栅区接触孔330中的导电金属可以选择为Cu，而填充在第一源/漏区接触孔240中的导电金属可以选择为Al；或者填充在第二源/漏区接触孔340和栅区接触孔330中的导电金属可以选择为Al，而填充在第一源/漏区接触孔240中的导电金属可以选择为Ti。 
由此，可以得到根据本实用新型的半导体器件。如前所述，第二源/漏区接触孔340和栅区接触孔330具有相同的刻蚀深度，因而，能够有效地降低接触孔与栅之间发生短路的可能性，而且刻蚀宽高比较为接近，因而，降低了对刻蚀工艺和接触孔填充的要求，同时，也减小了发生工艺缺陷的可能性。 
此外，根据本实用新型，第一源/漏区接触孔240与栅结构具有相同的高度，这样的结构使得形成第一源/漏区接触孔240的工艺过程更为容易，在这种情况下，完全是在平坦的表面上来执行光刻工艺。而且，这样的结构使得本实用新型与标准的替代栅工艺完全兼容。 
至此已经结合优选实施例对本实用新型进行了描述。应该理解，本领域技术人员在不脱离本实用新型的精神和范围的情况下，可以进行各种其它的改变、替换和添加。因此，本实用新型的范围不局限于上述特定实施例，而应由所附权利要求所限定。 

Claims (7)

1.一种半导体器件，其特征在于，所述半导体器件包括：
半导体衬底，具有形成在其上的源极/漏极区域和栅结构，所述栅结构包括金属栅；
第一层间介电层，沉积在所述半导体衬底上，具有形成在其中的第一源/漏区接触孔，所述第一源/漏区接触孔与所述源极/漏极区域相接触；以及
第二层间介电层，沉积在所述第一层间介电层上，具有形成在其中的第二源/漏区接触孔和栅区接触孔，所述第二源/漏区接触孔与所述第一源/漏区接触孔相接触，以及所述栅区接触孔与所述金属栅相接触，
所述第一源/漏区接触孔、所述第二源/漏区接触孔和所述栅区接触孔分别包括衬里和填充在其中的导电金属，
所述衬里由从以下材料组中选择的至少一种材料构成：TiN、TaN、Ta和Ti，以及
所述导电金属由从以下材料组中选择的至少一种材料构成：Ti、Al、TiAl、Cu和W；
其中所述第二源/漏区接触孔与所述栅区接触孔具有相同的深度。
2.根据权利要求1所述的半导体器件，其特征在于
所述第一源/漏区接触孔的宽度为15～100nm，
所述第二源/漏区接触孔的宽度为20～150nm，以及
所述栅区接触孔的宽度为20～150nm。
3.根据权利要求1所述的半导体器件，其特征在于，所述半导体器件还包括：
阻挡衬里，形成在所述第一层间介电层和所述半导体衬底之间。
4.根据权利要求3所述的半导体器件，其特征在于
所述阻挡衬里由Si3N4构成，且厚度为10～50nm。
5.根据权利要求1所述的半导体器件，其特征在于，所述半导体器件还包括：
阻挡层，形成在所述第一层间介电层和所述第二层间介电层之间。 
6.根据权利要求5所述的半导体器件，其特征在于
所述阻挡层由Si3N4构成，且厚度为10～50nm。
7.根据权利要求1所述的半导体器件，其特征在于
所述第一层间介电层的厚度为15～50nm，以及
所述第二层间介电层的厚度为25～90nm。 
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