WO2011032347A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2011032347A1
WO2011032347A1 PCT/CN2010/000836 CN2010000836W WO2011032347A1 WO 2011032347 A1 WO2011032347 A1 WO 2011032347A1 CN 2010000836 W CN2010000836 W CN 2010000836W WO 2011032347 A1 WO2011032347 A1 WO 2011032347A1
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Prior art keywords
contact hole
source
gate
dielectric layer
drain contact
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PCT/CN2010/000836
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English (en)
French (fr)
Inventor
尹海洲
朱慧珑
骆志炯
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中国科学院微电子研究所
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Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to GB1122197.5A priority Critical patent/GB2483414B/en
Priority to CN2010900007966U priority patent/CN202930362U/zh
Publication of WO2011032347A1 publication Critical patent/WO2011032347A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Field of the Invention relates to the field of semiconductors, and more particularly to semiconductor devices and methods of fabricating the same, and more particularly to a dual contact hole forming method for replacing a gate and a semiconductor device fabricated by the method. Background technique
  • FIG. 1 is a schematic view showing a semiconductor device fabricated according to a conventional process.
  • a semiconductor device fabricated according to a conventional process mainly includes: a S i substrate 100, an interlayer dielectric layer 180, a silicide region 110, a metal gate 120, source/drain contact holes 140, and gate contact holes.
  • a metal gate 120 is formed on the high-k dielectric layer 170, a high-k dielectric layer 170 is deposited on the S i substrate 100, and sidewalls 160 are formed around the high-k dielectric layer 170 and the metal gate 120;
  • a dielectric layer 180 is deposited on the Si substrate 100;
  • a silicide region 110 is formed on the Si substrate 100, embedded in the Si substrate 100;
  • source/drain contact holes 140 and gate contact holes 130 are formed in In the interlayer dielectric layer 180, the source/drain contact holes 140 are respectively in contact with the silicide region 110, and the gate contact holes 130 are in contact with the metal gate 120.
  • the source/drain contact hole 140 and the gate contact hole 130 respectively include a liner 125 and a conductive metal filled therein.
  • the etching depth Hca_ga te of the etching process performed to form the gate contact hole 130 is different from the etching depth Hca-sd of the etching process performed to form the source/drain contact hole 140.
  • the source/drain contact holes 140 have a smaller aspect ratio, and thus, during the formation of the source/drain contact holes 140, various process defects such as incomplete etch-through, voids in the plug-fill metal, and the like are more likely to occur.
  • the present invention proposes a double contact hole forming method for replacing a gate, thereby forming source/drain contact holes and gates having the same etching depth on the source/drain regions and the gate region.
  • the contact hole of the region prevents the formation of process defects while avoiding the short circuit between the source/drain contact hole and the gate; further, the present invention is compatible with the replacement gate process.
  • a dual contact hole forming method comprising the steps of: forming a source/drain region and a replacement gate structure on a semiconductor substrate, the replacement gate structure including a replacement gate; Depositing a first interlayer dielectric layer; planarizing the first interlayer dielectric layer to expose a replacement gate in the replacement gate structure; using a replacement gate process, removing the replacement gate, and depositing a metal gate; Using a photolithography process, a first source/drain contact hole opening is etched in the first interlayer dielectric layer, and a source formed on the semiconductor substrate is exposed at the bottom of the first source/drain contact hole opening a drain/drain region; sequentially depositing a liner and filling a conductive metal in the first source/drain contact hole opening to form a first source/drain contact hole; first in forming a first source/drain contact hole Depositing a second interlayer dielectric layer on the interlayer dielectric layer; etching a second source/drain
  • the first source/drain contact hole is narrower than the second source/drain contact hole and the gate contact hole. More preferably, the first source/drain contact hole has a width of 15 to 100 nm, the second source/drain contact hole has a width of 20 to 150 nm, and the gate contact hole has a width of 20 ⁇ 150nm o
  • the conductive metal filled in the second source/drain contact hole and the gate contact hole has a smaller resistivity than the conductive metal filled in the first source/drain contact hole.
  • the first interlayer dielectric layer is made of at least one selected from the group of materials below.
  • the electrical layer is composed of at least one material selected from the group consisting of undoped silicon oxide (SiO 2 ), various doped silicon oxides (such as borosilicate glass, borophosphosilicate glass, etc.) and silicon nitride. (Si 3 NJ.
  • the double contact hole forming method further comprises the steps of: integrally forming a barrier liner on the semiconductor substrate forming the source/drain region and the replacement gate structure before depositing the first interlayer dielectric layer.
  • the barrier village is composed of Si 3 N 4 and has a thickness of 10 to 50 nm.
  • the double contact hole forming method further comprises the steps of: forming a barrier integrally on the first interlayer dielectric layer on which the first source/drain contact hole is formed before depositing the second interlayer dielectric layer; Floor.
  • the barrier layer is composed of Si 3 N 4 and has a thickness of 10 to 50 nm.
  • the lining is composed of at least one material selected from the group consisting of TiN, TaN, Ta, and Ti
  • the conductive metal is composed of at least one material selected from the group consisting of Ti, Al , TiAl, (11 and
  • the first interlayer dielectric layer has a thickness of 15 to 50 nm
  • the second interlayer dielectric layer has a thickness of 25 to 90 nm.
  • a semiconductor device comprising: a semiconductor substrate having a source/drain region and a gate structure formed thereon, the gate structure including a metal gate; An electrical layer deposited on the semiconductor substrate having a first source/drain contact hole formed therein, the first source/drain contact hole being in contact with the source/drain region; a two-layer dielectric layer deposited on the first interlayer dielectric layer, having a second source/drain contact hole and a gate contact hole formed therein, the second source/drain contact hole and The first source/drain contact holes are in contact, and the gate contact holes are in contact with the metal gate.
  • the second source/drain contact hole has the same depth as the gate contact hole.
  • the first source/drain contact hole, the second source/drain contact hole, and the gate contact hole respectively include a liner and a conductive metal filled therein.
  • the conductive metal filled in the second source/drain contact hole and the gate contact hole has a smaller resistivity than the conductive metal filled in the first source/drain contact hole.
  • the village is composed of at least one material selected from the group consisting of TiN, TaN, Ta, and Ti
  • the conductive metal is composed of at least one material selected from the group consisting of Ti, Al, TiAl, Cu, and W.
  • the first source/drain contact hole is narrower than the second source/drain contact hole and the gate contact hole. More preferably, the first source/drain contact hole has a width of 15 to 100 nm, the second source/drain contact hole has a width of 20 to 150 nm, and the gate contact hole has a width of 20 ⁇ 150nm o
  • the first interlayer dielectric layer is composed of at least one material selected from the group consisting of undoped silicon oxide (S i0 2 ), various doped silicon oxides (such as borosilicate glass). , borophosphosilicate glass, etc.) and silicon nitride (Si 3 N 4 ), and the second interlayer dielectric layer is composed of at least one material selected from the group consisting of undoped silicon oxide (S I0 2 ), various doped silicon oxides (such as borosilicate glass, borophosphosilicate glass, etc.) and silicon nitride (S i 3 N 4 ).
  • the semiconductor device further includes: a barrier liner formed between the first interlayer dielectric layer and the semiconductor substrate.
  • the barrier lining is composed of Si 3 N 4 and has a thickness of 10 - 50 mn.
  • the semiconductor device further includes: a barrier layer formed between the first interlayer dielectric layer and the second interlayer dielectric layer.
  • the barrier layer is composed of Si 3 N 4 and has a thickness of 10 to 50 nm.
  • the first interlayer dielectric layer has a thickness of 15 to 50 nm
  • the second interlayer dielectric layer has a thickness of 25 to 90 nm.
  • the second source/drain contact hole and the gate contact hole have the same etching depth, and thus, the possibility of short circuit between the contact hole and the gate can be effectively reduced, and the etching width is relatively close.
  • the requirements for the etching process and contact hole filling are reduced, and at the same time, the possibility of occurrence of process defects is also reduced.
  • the present invention utilizes an alternate gate process that is compatible with typical alternative gate processes.
  • FIG. 1 is a schematic view showing a semiconductor device fabricated according to a conventional process
  • FIG. 14 is a schematic view showing a semiconductor device fabricated by the method of fabricating a semiconductor device proposed in accordance with the present invention.
  • the semiconductor device manufactured according to the proposed process of the present invention mainly comprises: a Si substrate 200, a first interlayer dielectric layer 280 (having a thickness of 15 to 50 nra), and a second interlayer dielectric layer 380 ( a thickness of 25 to 90 nm), a silicide region 210, a metal gate 220, a first source/drain contact hole 240 (having a width of 15 to 100 nra), a second source/drain contact hole 340 (having a width of 20 to 150 nm), and a gate contact hole 330 (having a width of 20 to 150 nm) in which a metal gate 220 is formed on the high-k dielectric layer 270 (thickness of 1 to 3 nm), and a high-k dielectric layer 270 is deposited on the Si substrate 200 at a high A SiN sidewall 260 (having a width of 10 to 40 nm) is formed around the k dielectric layer 270 and the
  • the first source/drain contact hole 240 is in contact with each other, and the gate contact hole 330 is in contact with the metal gate 220.
  • the first source/drain contact holes 240 respectively include a village 225 (having a thickness of 2 to 15 nm) and a conductive metal filled therein, and second source/drain contact holes 340 and
  • the gate contact holes 330 respectively include a village 325 (having a thickness of 2 to 15 nm) and a conductive metal filled therein.
  • the second source/drain contact hole 340 and the gate contact hole 330 have the same etching depth, and thus, the possibility of occurrence of a short circuit between the contact hole and the gate can be effectively reduced, and the etching width and height are compared. To be close, therefore, the requirements for the etching process and contact hole filling are reduced, and at the same time, the possibility of occurrence of process defects is also reduced.
  • each step of the method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to Figs. 2 to 14.
  • a silicide region 210 and a replacement gate structure are formed on the Si substrate 200.
  • the high-k dielectric layer 270 has a thickness of 1 to 3 nm
  • the polysilicon gate 320 has a thickness of 20 to 70 nm
  • the SiN sidewall 260 has a width of 10 to 40 nm in the horizontal direction as shown in the figure
  • the SiN cap layer The thickness is 15 ⁇ 40nm.
  • This step is also part of the conventional process where polysilicon gate 320 is formed as an alternative to the metal gate.
  • a barrier liner (for example, may be composed of Si 3 N 4 ) (not shown) may be integrally formed on the structure shown in FIG. 2 before the step shown in FIG. 3 is performed.
  • the barrier lining has a thickness of 10 to 50 nm.
  • a first interlayer dielectric layer 280 is deposited on the Si substrate 200 on which the silicide region 210 and the replacement gate structure have been formed.
  • undoped silicon oxide (SiO 2 ) various doped silicon oxides (such as borosilicate glass, borophosphosilicate glass, etc.) and silicon nitride (Si 3 N 4 ) can be used as the first interlayer.
  • the constituent material of the electric layer 280 is subjected to a chemical mechanical planarization (CMP) process to expose the SiN cap layer in place of the gate structure.
  • CMP chemical mechanical planarization
  • an additional CMP process or a reactive ion etching (RIE) process for SiN is performed to remove the SiN cap layer, exposing the polysilicon gate 320 in place of the gate structure.
  • the polysilicon gate 320 is removed by wet etching or dry etching.
  • a metal gate 220 is deposited by a typical replacement gate process. After this step is completed, the polysilicon gate 320 as a replacement gate has been completely replaced by the metal gate 220.
  • a photoresist mask FIG.
  • the contact hole opening exposes a silicide region 210 (Fig. 9) on the Si substrate 200 at the bottom of the contact hole opening.
  • a barrier village (not shown) is included, etching is required to penetrate the barrier village located on the bottom of the contact hole opening, the silicide region 210, to expose the silicide region 210.
  • a metal plug is deposited in the contact hole opening to form the first source/drain contact hole 240 such that the first source/drain contact hole 240 respectively has a silicide region 210 at a corresponding position below it.
  • a village 225 for example, TiN, TaN, Ta or Ti, typically between about 2 nm and about 15 nm thick
  • a conductive metal for example, Ti, Al, TiAl, Cu
  • W, etc. and finally perform the metal CMP process.
  • the formation process of the first source/drain contact hole 240 is the same as or similar to the conventional process. According to the present invention, the width of the first source/drain contact hole 240 (horizontal horizontal width) is 15 to 100 nm.
  • a barrier layer (for example, may be composed of S i 3 N 4 ) may be integrally formed on the structure shown in FIG. 10 before the step shown in FIG. 11 is performed (not shown).
  • the thickness of the barrier layer is 10 to 50 nm.
  • a second interlayer dielectric layer 380 is deposited on the first interlayer dielectric layer 280 on which the first source/drain contact holes 240 and the metal gate 220 have been formed.
  • undoped silicon oxide (SiO 2 ) various doped silicon oxides (such as borosilicate glass, borophosphosilicate glass, etc.) and silicon nitride (Si 3 N 4 ) can be used as the second interlayer.
  • the constituent material of the electric layer 380 Due to before (figure The CMP process performed in 10), the two-layer dielectric layer 380 has a flat upper surface. Then, as shown in FIGS. 12 and 13, a photoresist mask (FIG. 12) is formed by a photolithography process, and a photolithography and degelation process is performed to form a predetermined position in the second interlayer dielectric layer 380.
  • the contact hole opening exposes a first source/drain contact hole 240 and a metal gate 220 (Fig. 13) in the first interlayer dielectric layer 280 at the bottom of the contact hole opening.
  • etching is required to penetrate the barrier lining at the bottom of the contact hole opening, the first source/drain contact hole 240, and the metal gate 220 to expose the first source/ The drain region contacts the via 240 and the metal gate 220.
  • a metal plug is deposited in the contact hole opening to form a second source/drain contact hole 340 and a gate contact hole 330, so that the second source/drain contact hole 340 respectively corresponds to the lower side thereof.
  • the first source/drain contact holes 240 of the position are in contact, and the gate contact holes 330 are brought into contact with the metal gate 220.
  • a liner 325 (e.g., TiN, TaN, Ta, or Ti, typically between about 2 nm and about 15 nm thick) is deposited first, followed by deposition of a conductive metal (e.g., Ti, Al, TiAl, Cu). , W, etc., and finally perform the metal CMP process.
  • the formation process of the second source/drain contact hole 340 and the gate contact hole 330 is the same as or similar to the conventional process. According to the present invention, the width of the second source/drain contact hole 340 (the horizontal width in the drawing) is 20 - 150 nm; the width of the gate contact hole 330 (the horizontal width in the drawing) is 20 - 150 nm.
  • the conductive metal may be selected such that the conductive metal filled in the second source/drain contact hole 340 and the gate contact hole 330 has a specific filling in the first source/drain contact hole 240
  • the conductive metal has a small resistivity.
  • the conductive metal filled in the second source/drain contact hole 340 and the gate contact hole 330 may be selected as Cu, and the conductive metal filled in the first source/drain contact hole 240 may be selected as A1;
  • the conductive metal filled in the second source/drain contact hole 340 and the gate contact hole 330 may be selected as Al, and the conductive metal filled in the first source/drain contact hole 240 may be selected as Ti.
  • the second source/drain contact hole 340 and the gate contact hole 330 have the same etching depth, and thus can be effective
  • the ground is reduced in the possibility of short circuit between the contact hole and the gate, and the etching width is relatively close, thereby reducing the requirements for the etching process and the contact hole filling, and also reducing the possibility of process defects. .
  • the first source/drain contact hole 240 has the same height as the gate structure, and such a structure makes the process of forming the first source/drain contact hole 240 easier, in which case The photolithography process is performed entirely on a flat surface. Moreover, such a structure allows the invention to be fully compatible with standard replacement gate processes.

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Description

半导体器件及其制造方法 技术领域
本发明涉及半导体领域， 尤其涉及半导体器件及其制造方法， 更具 体地， 涉及一种用于替代栅的双接触孔形成方法以及利用所述方法制造 出的半导体器件。 背景技术
随着半导体器件的尺寸越来越小， 层间触点和接触孔（CA )也越来 越小， 且相互间的距离也随之减小。 利用传统工艺制造较小的触点和接 触孔存在以下一些问题： （ 1 )由于栅上的刻蚀深度与源 /漏区中的刻蚀深 度不同，容易造成接触孔与栅之间的短路； （2 )由于源 /漏区中的刻蚀深 度较深且开口较小（即，具有较小的宽高比），可能会引起无法完全刻通、 插头填充金属中出现空洞等多种工艺缺陷， 从而限制了工艺的选择性， 而且导致了寄生电阻的增大。
以下， 将结合图 1， 对传统工艺所引起的问题进行详细描述。 图 1 是示出了根据传统工艺制造的半导体器件的示意图。 如图 1所示， 根据 传统工艺制造的半导体器件主要包括： S i衬底 100、 层间介电层 180、 硅化物区域 110、 金属栅 120、 源 /漏区接触孔 140和栅区接触孔 130, 其中金属栅 120形成在高 k介电层 170上， 高 k介电层 170沉积在 S i 衬底 100上， 在高 k介电层 170和金属栅 120周围形成有側壁 160; 层 间介电层 180沉积在 S i衬底 100上；硅化物区域 110形成在 S i村底 100 上， 嵌入在 S i衬底 100中； 源 /漏区接触孔 140和栅区接触孔 130形成 在层间介电层 180中，源 /漏区接触孔 140分别与硅化物区域 110相接触， 栅区接触孔 130与金属栅 120相接触。源 /漏区接触孔 140和栅区接触孔 130分别包括衬里 125和填充在其中的导电金属。 如图 1所示， 为了形 成栅区接触孔 130而执行的刻蚀工艺的刻蚀深度 Hca_ga te与为了形成源 /漏区接触孔 140而执行的刻蚀工艺的刻蚀深度 Hca- sd不同，源 /漏区接 触孔 140具有更小的宽高比， 因此在源 /漏区接触孔 140的形成过程中， 更容易产生无法完全刻通、 插头填充金属中出现空洞等多种工艺缺陷。 而且， 由于源 /漏区接触孔 140的刻蚀工艺要求较高， 极有可能导致源. / 漏区接触孔 140与金属栅 120之间的短路（图 1中的虛线所示）。 发明内容
考虑到传统工艺的上述缺陷， 本发明提出了一种用于替代栅的双接 触孔形成方法， 从而在源 /漏区和栅区上形成具有相同刻蚀深度的源 /漏 区接触孔和栅区接触孔， 在避免了源 /漏区接触孔与栅之间的短路的同 时， 防止了工艺缺陷的形成； 此外， 本发明与替代栅工艺兼容。 才艮据本发明的第一方案， 提出了一种双接触孔形成方法， 包括以下 步骤： 在半导体衬底上形成源极 /漏极区域和替代栅结构， 所述替代栅结 构包括替代栅； 沉积第一层间介电层； 对第一层间介电层进行平坦化处 理， 以暴露出所述替代栅结构中的替代栅； 采用替代栅工艺， 去除替代 栅， 并沉积形成金属栅； 采用光刻工艺， 在第一层间介电层中刻蚀出第 一源 /漏区接触孔开口， 在第一源 /漏区接触孔开口的底部， 暴露出形成 在半导体衬底上的源极 /漏极区域； 在第一源 /漏区接触孔开口中顺序沉 积衬里和填充导电金属， 以形成第一源 /漏区接触孔； 在形成有第一源 / 漏区接触孔的第一层间介电层上沉积第二层间介电层； 采用光刻工艺， 在第二层间介电层中刻蚀出第二源 /漏区接触孔开口和栅区接触孔开口， 在第二源 /漏区接触孔开口的底部， 暴露出第一源 /漏区接触孔， 以及在 栅区接触孔开口的底部，暴露出金属栅； 以及在第二源 /漏区接触孔开口 和栅区接触孔开口中顺序沉积衬里和填充导电金属，以形成第二源 /漏区 接触孔和栅区接触孔。
优选地， 所述第一源 /漏区接触孔比所述第二源 /漏区接触孔和所述 栅区接触孔窄。更优选地，所述第一源 /漏区接触孔的宽度为 15 - l OOnm, 所述第二源 /漏区接触孔的宽度为 20 ~ 150mn， 以及所述栅区接触孔的宽 度为 20 ~ 150nmo
优选地， 填充在所述第二源 /漏区接触孔和所述栅区接触孔中的导 电金属具有比填充在所述第一源 /漏区接触孔中的导电金属小的电阻率。
优选地， 所述第一层间介电层由从以下材料组中选择的至少一种材 料构成： 未掺杂的氧化硅（Si02 )、 掺杂的氧化硅（如硼硅玻璃、 硼磷硅 玻璃等）和氮化硅（ Si3N4 ), 以及所述第二层间介电层由从以下材料组中 选择的至少一种材料构成： 未掺杂的氧化硅（Si02 )、 各种掺杂的氧化硅 (如硼硅玻璃、 硼磷硅玻璃等）和氮化硅（Si3NJ。
优选地， 所述双接触孔形成方法还包括以下步骤： 在沉积第一层间 介电层之前，在形成有源极 /漏极区域和替代栅结构的半导体衬底上，整 体形成阻挡衬里。其中，所述阻挡村里由 Si3N4构成，且厚度为 10 ~ 50nm。
优选地， 所述双接触孔形成方法还包括以下步骤： 在沉积第二层间 介电层之前，在形成有第一源 /漏区接触孔的第一层间介电层上， 整体形 成阻挡层。 其中， 所述阻挡层由 Si3N4构成， 且厚度为 10 ~ 50nm。
优选地， 所述衬里由从以下材料组中选择的至少一种材料构成： TiN、 TaN、 Ta和 Ti， 以及所述导电金属由从以下材料组中选择的至少一 种材料构成： Ti、 Al、 TiAl、 （11和
优选地， 所述第一层间介电层的厚度为 15 ~ 50nm, 以及所述第二层 间介电层的厚度为 25 ~ 90nm。 根据本发明的第二方案， 提出了一种半导体器件， 包括： 半导体衬 底，具有形成在其上的源极 /漏极区域和栅结构，所述栅结构包括金属栅； 第一层间介电层，沉积在所述半导体村底上，具有形成在其中的第一源 / 漏区接触孔， 所述第一源 /漏区接触孔与所述源极 /漏极区域相接触； 以 及第二层间介电层， 沉积在所述第一层间介电层上， 具有形成在其中的 第二源 /漏区接触孔和栅区接触孔， 所述第二源 /漏区接触孔与所述第一 源 /漏区接触孔相接触， 以及所述栅区接触孔与所述金属栅相接触。
优选地， 所述第二源 /漏区接触孔与所述栅区接触孔具有相同的深 度。
优选地， 所述第一源 /漏区接触孔、 所述第二源 /漏区接触孔和所述 栅区接触孔分别包括衬里和填充在其中的导电金属。 更优选地， 填充在 所述第二源 /漏区接触孔和所述栅区接触孔中的导电金属具有比填充在 所述第一源 /漏区接触孔中的导电金属小的电阻率。更优选地，所述村里 由从以下材料组中选择的至少一种材料构成： TiN、 TaN、 Ta和 Ti , 以及 所述导电金属由从以下材料组中选择的至少一种材料构成： Ti、Al、TiAl、 Cu和 W。
优选地， 所述第一源 /漏区接触孔比所述第二源 /漏区接触孔和所述 栅区接触孔窄。更优选地，所述第一源 /漏区接触孔的宽度为 15 ~ l OOnm, 所述第二源 /漏区接触孔的宽度为 20 ~ 150nm， 以及所述栅区接触孔的宽 度为 20 ~ 150nmo
优选地， 所述第一层间介电层由从以下材料组中选择的至少一种材 料构成： 未掺杂的氧化硅（S i02 )、 各种掺杂的氧化硅（如硼硅玻璃、 硼 磷硅玻璃等）和氮化硅（ Si3N4 )， 以及所述第二层间介电层由从以下材料 组中选择的至少一种材料构成： 未掺杂的氧化硅（S i02 )、 各种掺杂的氧 化硅（如硼硅玻璃、 硼磷硅玻璃等）和氮化硅（S i 3N4 )。
优选地， 所述半导体器件还包括： 阻挡衬里， 形成在所述第一层间 介电层和所述半导体衬底之间。 其中， 所述阻挡衬里由 Si3N4构成， 且厚 度为 10 - 50mn。
优选地， 所述半导体器件还包括： 阻挡层， 形成在所述第一层间介 电层和所述第二层间介电层之间。 其中， 所述阻挡层由 Si3N4构成， 且厚 度为 10 ~ 50nm。
优选地， 所述第一层间介电层的厚度为 15 ~ 50nm, 以及所述第二层 间介电层的厚度为 25 ~ 90nm。 根据本发明， 第二源 /漏区接触孔和栅区接触孔具有相同的刻蚀深 度， 因而， 能够有效地降低接触孔与栅之间发生短路的可能性， 而且刻 蚀宽高比较为接近， 因而， 降低了对刻蚀工艺和接触孔填充的要求， 同 时， 也减小了发生工艺缺陷的可能性。 此外， 本发明利用替代栅工艺， 与典型的替代栅流程兼容。 附图说明
通过下面结合附图说明本发明的优选实施例， 将使本发明的上述及 其它目的、 特征和优点更加清楚， 其中：
图 1是示出了根据传统工艺制造的半导体器件的示意图； 以及 的示意图，其中图 14示出了根据本发明所提出的半导体器件制造方法制 造完成的半导体器件。
应当注意的是， 本说明书附图并非按照比例绘制， 而仅为示意性的 目的， 因此， 不应被理解为对本发明范围的任何限制和约束。在附图中， 相似的组成部分以相似的附图标号标识。 具体实施方式
下面参照附图对本发明的优选实施例进行详细说明， 在描述过程中 省略了对于本发明来说是不必要的细节和功能， 以防止对本发明的理解 造成混淆。 首先， 参考图 14, 对根据本发明所提出的工艺制造的半导体器件进 行详细描述。图 14是示出了根据本发明所提出的半导体器件制造方法制 造完成的半导体器件的示意图。
如图 14 所示， 根据本发明所提出的工艺制造的半导体器件主要包 括： Si衬底 200、 第一层间介电层 280 (厚度为 15~50nra)、 第二层间介 电层 380 (厚度为 25~90nm)、 硅化物区域 210、 金属栅 220、 第一源 / 漏区接触孔 240 (宽度为 15~100nra)、 第二源 /漏区接触孔 340 (宽度为 20 - 150nm)和栅区接触孔 330 (宽度为 20~150nm)， 其中金属栅 220 形成在高 k介电层 270 (厚度为 1 ~ 3nm)上， 高 k介电层 270沉积在 Si 衬底 200上， 在高 k介电层 270和金属栅 220周围形成有 SiN側壁 260 (宽度为 10~40nm); 第一层间介电层 280沉积在 Si村底 200上； 第二 层间介电层 380沉积在第一层间介电层 280上； 硅化物区域 210形成在 Si衬底 200上， 嵌入在 Si衬底 200中； 第一源 /漏区接触孔 240形成在 第一层间介电层 280中，且分别与硅化物区域 210相接触； 第二源 /漏区 接触孔 340和栅区接触孔 330形成在第二层间介电层 380中， 第二源 / 漏区接触孔 340分别与第一源 /漏区接触孔 240相接触，栅区接触孔 330 与金属栅 220相接触。 第一源 /漏区接触孔 240分别包括村里 225 (厚度 为 2~15nm)和填充在其中的导电金属， 以及第二源 /漏区接触孔 340和 栅区接触孔 330分别包括村里 325 (厚度为 2 ~ 15nm )和填充在其中的导 电金属。
根据本发明， 第二源 /漏区接触孔 340和栅区接触孔 330具有相同 的刻蚀深度， 因而， 能够有效地降低接触孔与栅之间发生短路的可能性， 而且刻蚀宽高比较为接近， 因而， 降低了对刻蚀工艺和接触孔填充的要 求， 同时， 也减小了发生工艺缺陷的可能性。 接下来， 将结合图 2 ~ 14， 对根据本发明的半导体器件制造方法的 各个步骤进行详细描述。
首先， 如图 2所示， 在 Si衬底 200上形成硅化物区域 210和替代 栅结构 （高 k介电层 270、 多晶硅栅 320、 围绕和覆盖高 k介电层 270 和多晶硅栅 320的 SiN侧壁 260和 SiN盖层）。 作为本发明的示例， 高 k 介电层 270的厚度为 1 ~ 3nm， 多晶硅栅 320的厚度为 20 ~ 70mn, SiN侧 壁 260在图示水平方向上的宽度为 10 ~ 40nm, SiN盖层的厚度为 15 ~ 40nm。 这一步骤同样是传统工艺的一部分， 这里形成了多晶硅栅 320以 作为替代金属栅的替代栅。
在形成了图 2所示的结构之后， 执行图 3所示的步骤之前， 可以在 图 2所示的结构上整体形成一阻挡衬里 （例如， 可由 Si3N4构成）（未示 出）， 阻挡衬里的厚度为 10 ~ 50nm。 然后， 如图 3所示， 在已形成硅化物区域 210和替代栅结构的 Si 衬底 200上沉积第一层间介电层（ Inter Layer Dielectr ic layer ) 280。 例如， 未掺杂的氧化硅（Si02 )、 各种掺杂的氧化硅（如硼硅玻璃、 硼磷 硅玻璃等）和氮化硅（Si3N4 )等可以作为第一层间介电层 280的构成材 料。 接下来， 如图 4所示， 对第一层间介电层 280进行化学机械平坦化 ( CMP )处理， 从而暴露出替代栅结构的 SiN盖层。
然后， 如图 5所示， 执行另外的 CMP处理或针对 SiN的反应离子刻 蚀 （RIE )处理， 去除 SiN盖层， 暴露出替代栅结构的多晶硅栅 320。 之后， 如图 6所示， 采用湿法刻蚀或干法刻蚀， 去除多晶硅栅 320。 接下来，如图 7所示，采用典型的替代栅工艺，沉积形成金属栅 220。 在完成这一步骤之后，作为替代栅的多晶硅栅 320已经完全被金属栅 220 所取代。 然后， 如图 8和 9所示， 采用光刻工艺， 形成光刻胶掩模（图 8 )， 并执行光刻、 去胶工艺， 在第一层间介电层 280中的预定位置， 形成接 触孔开口，在接触孔开口的底部，暴露出位于 Si衬底 200上的硅化物区 域 210 (图 9 )。 在包含阻挡村里 （未示出） 的情况下， 需要刻蚀穿透位 于接触孔开口的底部、 硅化物区域 210上的阻挡村里， 以暴露出硅化物 区域 210。 之后， 如图 10所示， 在接触孔开口中沉积形成金属插头， 从而形 成第一源 /漏区接触孔 240, 使得第一源 /漏区接触孔 240分别与其下方 相应位置的硅化物区域 210相接触。 在这一步骤中， 首先沉积村里 225 (例如， TiN、 TaN、 Ta或 Ti , 典型地， 厚度在大约 2nm到大约 15nm之 间）， 然后再沉积导电金属（例如， Ti、 Al、 TiAl、 Cu、 W等）， 最后再 执行金属的 CMP工艺。第一源 /漏区接触孔 240的形成工艺与传统工艺相 同或类似。根据本发明，第一源 /漏区接触孔 240的宽度（图示水平宽度） 为 15 ~ 100nm。
在形成了图 10所示的结构之后， 执行图 11所示的步骤之前， 可以 在图 10所示的结构上整体形成一阻挡层（例如， 可由 S i3N4构成）（未示 出）， 阻挡层的厚度为 10 ~ 50nm。 接下来， 如图 11所示， 在已形成第一源 /漏区接触孔 240和金属栅 220的第一层间介电层 280上沉积第二层间介电层 380。例如， 未掺杂的 氧化硅（Si02 )、 各种掺杂的氧化硅（如硼硅玻璃、 硼磷硅玻璃等）和氮 化硅（Si3N4 )等可以作为第二层间介电层 380的构成材料。 由于之前（图 10 ) 中所执行的 CMP工艺， ^二层间介电层 380具有平坦的上表面。 然后，如图 12和 13所示，采用光刻工艺，形成光刻胶掩模（图 12 ), 并执行光刻、 去胶工艺， 在第二层间介电层 380中的预定位置， 形成接 触孔开口， 在接触孔开口的底部， 暴露出位于第一层间介电层 280中的 第一源 /漏区接触孔 240和金属栅 220 (图 13 )。在包含阻挡层（未示出） 的情况下， 需要刻蚀穿透位于接触孔开口的底部、 第一源 /漏区接触孔 240和金属栅 220上的阻挡衬里， 以暴露出第一源 /漏区接触孔 240和金 属栅 220。 最后， 如图 14 所示， 在接触孔开口中沉积形成金属插头， 从而形 成第二源 /漏区接触孔 340和栅区接触孔 330, 使得第二源 /漏区接触孔 340分别与其下方相应位置的第一源 /漏区接触孔 240相接触， 以及使得 栅区接触孔 330与金属栅 220相接触。在这一步骤中，首先沉积衬里 325 (例如， TiN、 TaN、 Ta或 Ti , 典型地， 厚度在大约 2nm到大约 15nm之 间）， 然后再沉积导电金属（例如， Ti、 Al、 TiAl、 Cu、 W等）， 最后再 执行金属的 CMP工艺。第二源 /漏区接触孔 340和栅区接触孔 330的形成 工艺与传统工艺相同或类似。根据本发明， 第二源 /漏区接触孔 340的宽 度（图示水平宽度） 为 20 - 150nm; 栅区接触孔 330的宽度（图示水平 宽度） 为 20 - 150nm。
此外， 根据本发明， 可以对导电金属进行选择， 从而使填充在第二 源 /漏区接触孔 340和栅区接触孔 330中的导电金属具有比填充在第一源 /漏区接触孔 240中的导电金属小的电阻率。 例如， 填充在第二源 /漏区 接触孔 340和栅区接触孔 330中的导电金属可以选择为 Cu, 而填充在第 一源 /漏区接触孔 240中的导电金属可以选择为 A1; 或者填充在第二源 / 漏区接触孔 340和栅区接触孔 330中的导电金属可以选择为 Al， 而填充 在第一源 /漏区接触孔 240中的导电金属可以选择为 Ti。 由此， 可以得到根据本发明的半导体器件。 如前所述， 第二源 /漏 区接触孔 340和栅区接触孔 330具有相同的刻蚀深度， 因而， 能够有效 地降低接触孔与栅之间发生短路的可能性， 而且刻蚀宽高比较为接近， 因而， 降低了对刻蚀工艺和接触孔填充的要求， 同时， 也减小了发生工 艺缺陷的可能性。
此外， 根据本发明， 第一源 /漏区接触孔 240 与栅结构具有相同的 高度， 这样的结构使得形成第一源 /漏区接触孔 240 的工艺过程更为容 易， 在这种情况下， 完全是在平坦的表面上来执行光刻工艺。 而且， 这 样的结构使得本发明与标准的替代栅工艺完全兼容。
至此已经结合优选实施例对本发明进行了描述。 应该理解， 本领域 技术人员在不脱离本发明的精神和范围的情况下， 可以进行各种其它的 改变、 替换和添加。 因此， 本发明的范围不局限于上述特定实施例， 而 应由所附权利要求所限定。

Claims

权 利 要 求 书
1. 一种双接触孔形成方法， 包括以下步骤：
在半导体衬底上形成源极 /漏极区域和替代栅结构， 所述替代栅结 构包括替代栅；
沉积第一层间介电层；
对第一层间介电层进行平坦化处理， 以暴露出所述替代栅结构中的 替代栅；
采用替代栅工艺， 去除替代栅， 并沉积形成金属栅；
采用光刻工艺， 在第一层间介电层中刻蚀出第一源 /漏区接触孔开 口，在第一源 /漏区接触孔开口的底部，暴露出形成在半导体衬底上的源 极 /漏极区域；
在第一源 /漏区接触孔开口中顺序沉积衬里和填充导电金属， 以形 成第一源 /漏区接触孔；
在形成有第一源 /漏区接触孔的第一层间介电层上沉积第二层间介 电层；
采用光刻工艺， 在第二层间介电层中刻蚀出第二源 /漏区接触孔开 口和栅区接触孔开口，在第二源 /漏区接触孔开口的底部，暴露出第一源 /漏区接触孔， 以及在栅区接触孔开口的底部， 暴露出金属栅； 以及
在第二源 /漏区接触孔开口和栅区接触孔开口中顺序沉积衬里和填 充导电金属， 以形成第二源 /漏区接触孔和栅区接触孔。
2. 根据权利要求 1所述的双接触孔形成方法， 其中
' 所述第一源 /漏区接触孔的宽度为 15 - l OOnm,
所述第二源 /漏区接触孔的宽度为 20 ~ 150nra， 以及
所述栅区接触孔的宽度为 20 - 150nm。
3. 根据权利要求 1所述的双接触孔形成方法， 其中
填充在所述第二源 /漏区接触孔和所述栅区接触孔中的导电金属具 有比填充在所述第一源 /漏区接触孔中的导电金属小的电阻率。
4. 根据权利要求 1所述的双接触孔形成方法， 还包括以下步骤： 在沉积第一层间介电层之前， 在形成有源极 /漏极区域和替代栅结 构的半导体衬底上， 整体形成阻挡衬里。
5. 根据权利要求 4所述的双接触孔形成方法， 其中
所述阻挡村里由 Si3N4构成， 且厚度为 10~50ηπι。
6. 根据权利要求 1所述的双接触孔形成方法， 还包括以下步骤： 在沉积第二层间介电层之前， 在形成有第一源 /漏区接触孔的第一 层间介电层上， 整体形成阻挡层。
7. 根据权利要求 6所述的双接触孔形成方法， 其中
所述阻挡层由 Si3N4构成， 且厚度为 10~50nm。
8. 根据权利要求 1所述的双接触孔形成方法， 其中
所述衬里由从以下材料组中选择的至少一种材料构成： TiN、 TaN、
Ta和 Ti, 以及
所述导电^ r属由从以下材料组中选择的至少一种材料构成： Ti、 AI、
TiAK C W。
9. 根据权利要求 1所述的双接触孔形成方法， 其中
所述替代栅是多晶硅栅。
10. 根据权利要求 1所述的双接触孔形成方法， 其中
所述第一层间介电层的厚度为 15 50nm， 以及
所述第二层间介电层的厚度为 25 - 90nm。
11. 一种半导体器件， 包括：
半导体村底， 具有形成在其上的源极 /漏极区域和栅结构， 所述栅 结构包括金属栅；
第一层间介电层， 沉积在所述半导体衬底上， 具有形成在其中的第 一源 /漏区接触孔， 所述第一源 /漏区接触孔与所述源极 /漏极区域相接 触； 以及
第二层间介电层， 沉积在所述第一层间介电层上， 具有形成在其中 的第二源 /漏区接触孔和栅区接触孔， 所述第二源 /漏区接触孔与所述第 一源 /漏区接触孔相接触， 以及所述栅区接触孔与所述金属栅相接触。
12. 根据权利要求 11 所述的半导体器件， 其中所述第二源 /漏区 接触孔与所述栅区接触孔具有相同的深度。
13. 根据权利要求 11所述的半导体器件， 其中 所述第一源 /漏区接触孔、 所述第二源 /漏区接触孔和所述栅区接触 孔分别包括衬里和填充在其中的导电金属。
14. 根据权利要求 13所述的半导体器件， 其中
所述衬里由从以下材料组中选择的至少一种材料构成： TiN、 TaN、 Ta和 Ti， 以及
所述导电金属由从以下材料组中选择的至少一种材料构成： Ti、 Al、 TiAl、 C W。
15. 根据权利要求 11所述的半导体器件， 其中
所述第一源 /漏区接触孔的宽度为 15~ 100nm，
所述第二源 /漏区接触孔的宽度为 20~150nm， 以及
所述栅区接触孔的宽度为 20~ 150nm。
16. 根据权利要求 11所述的半导体器件， 还包括：
阻挡村里， 形成在所述第一层间介电层和所述半导体衬底之间。
17. 根据权利要求 16所述的半导体器件， 其中
所述阻挡衬里由 Si3N4构成， 且厚度为 10~50nm。
18. 根据权利要求 11所述的半导体器件， 还包括：
阻挡层， 形成在所述第一层间介电层和所述第二层间介电层之间。
19. 根据权利要求 18所述的半导体器件， 其中
所述阻挡层由 Si3N4构成， 且厚度为 10~50nm。
20. 根据权利要求 11所述的半导体器件， 其中
所述第一层间介电层的厚度为 15- 50nm, 以及
所述第二层间介电层的厚度为 25~90nm。
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CN1967845A (zh) * 2005-11-15 2007-05-23 东部电子股份有限公司 半导体器件及其制造方法
US20070257323A1 (en) * 2006-05-05 2007-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked contact structure and method of fabricating the same

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CN102738234A (zh) * 2011-04-15 2012-10-17 中国科学院微电子研究所 半导体器件及其制造方法
CN105206667A (zh) * 2014-06-13 2015-12-30 中芯国际集成电路制造(上海)有限公司 接触插塞、mos、鳍式场效应晶体管，及其形成方法
CN105206667B (zh) * 2014-06-13 2018-08-10 中芯国际集成电路制造(上海)有限公司 接触插塞、mos、鳍式场效应晶体管，及其形成方法
US11532510B2 (en) * 2018-09-24 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts and interconnect structures in field-effect transistors

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