JP2010045343A - 半導体デバイス - Google Patents
半導体デバイス Download PDFInfo
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- JP2010045343A JP2010045343A JP2009166622A JP2009166622A JP2010045343A JP 2010045343 A JP2010045343 A JP 2010045343A JP 2009166622 A JP2009166622 A JP 2009166622A JP 2009166622 A JP2009166622 A JP 2009166622A JP 2010045343 A JP2010045343 A JP 2010045343A
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Abstract
【解決手段】基板1上の第1活性層3と、第1活性層3の上に、該第1活性層3に比較して高いバンドギャップを有する第2活性層4配設し、実質的にGaを含まないで少なくともAlを含む第2活性層4と、第2活性層4の少なくとも一部の上のゲート絶縁層5であって、第2活性層4の少なくとも一部を熱酸化して形成されたゲート絶縁層5と、ゲート絶縁層5の少なくとも一部の上のゲート電極6と、第2活性層4の上のソース電極7およびドレイン電極8とを含み、前記半導体デバイス10は、更に、動作時でゲート電極6とソース電極7が同電圧の場合、第1活性層3と第2活性層4の間で、ゲート電極6の外側でゲート電極6の位置以外に、2次元電子ガス2DEG層を含む。
【選択図】図1
Description
基板上の第1活性層と、
第1活性層の上の第2活性層であって、第1活性層に比較して高いバンドギャップを有し、実質的にGaを含まない第2活性層と、
第2活性層の少なくとも一部の上のゲート絶縁層であって、第2活性層の少なくとも一部を熱酸化して形成され、これにより第2活性層の上の部分を消費し、第2活性層の厚みを減らし、2DEGが部分的に空乏化されるゲート絶縁層と、
ゲート絶縁層の少なくとも一部の上のゲート電極と、
第2活性層の上のソース電極およびドレイン電極と、を含み、
動作状態でゲート電極とソース電極が同じ電圧の場合、半導体デバイスは、更に、ゲート電極の場所の外側のみでゲート電極の位置ではない第1活性層と第2活性層の間に、2次元電子ガス(2DEG)層を含む。
基板の上に第1活性層を提供する工程と、
第1活性層の上に第2活性層を提供する工程であって、第1活性層に比較して高いバンドギャップを有し、実質的にGaを含まない第2活性層を提供する工程と、
第2活性層の少なくとも一部を熱酸化により酸化してゲート酸化層を形成し、これにより第2活性層の上の部分を消費し、第2活性層の厚みを減らし、2DEGを部分的に空乏化する工程と、
ゲート絶縁層の上にゲート電極を提供する工程と、
第2活性層の第2領域の上に、ソース電極およびドレイン電極を提供する工程と、を含み、
第1活性層および第2活性層を提供する工程は、動作状態で、ゲート電極とソース電極が同じ電圧の場合に、半導体デバイスが、更に、ゲート電極の場所の外側のみでゲート電極の位置ではない第1活性層と第2活性層の間に2次元電子ガス層を含むように行われる。
基板上の第1活性層と、
第1活性層の上の第2活性層であって、第1活性層に比較して高いバンドギャップを有し、実質的にGaを含まない第2活性層と、
第2活性層の少なくとも一部の上のゲート絶縁層であって、第2活性層の少なくとも一部を熱酸化して形成され、これにより第2活性層の上の部分を消費し、第2活性層の厚みを減らし、2DEGが部分的に空乏化されるゲート絶縁層と、
ゲート絶縁層の少なくとも一部の上のゲート電極と、
第2活性層の上のソース電極およびドレイン電極と、を含み、
動作状態でゲート電極とソース電極が同じ電圧の場合、半導体デバイスは、更に、ゲート電極の場所の外側のみでゲート電極の位置ではない第1活性層と第2活性層の間に、2次元電子ガス(2DEG)層を含む。
基板の上に第1活性層を提供する工程と、
第1活性層の上に第2活性層を提供する工程であって、第1活性層に比較して高いバンドギャップを有し、実質的にGaを含まない第2活性層を提供する工程と、
第2活性層の少なくとも一部を熱酸化により酸化してゲート酸化層を形成し、これにより第2活性層の上の部分を消費し、第2活性層の厚みを減らし、2DEGを部分的に空乏化する工程と、
ゲート絶縁層の上にゲート電極を提供する工程と、
第2活性層の第2領域の上に、ソース電極およびドレイン電極を提供する工程と、を含み、
第1活性層および第2活性層を提供する工程は、動作状態で、ゲート電極とソース電極が同じ電圧の場合に、半導体デバイスが、更に、ゲート電極の場所の外側のみでゲート電極の位置ではない第1活性層と第2活性層の間に2次元電子ガス層を含むように行われる。
この例ではGaN層であるバッファ層2を上部に有する基板1と、
バッファ層2の上部層により形成された第1活性層3と、
第1活性層3の上の第2活性層4であって、この例では、InxAl1−xN層(xは0.17)である第2活性層4と、
第2活性層4の少なくとも一部の上のゲート絶縁層5であって、第2活性層4の少なくとも一部を熱酸化して形成したゲート絶縁層5と、
ゲート絶縁層5の上の、ゲートコンタクトとも呼ばれるゲート電極6と、
第2活性層4の上の、ソースコンタクトとも呼ばれるソース電極7と、ドレインコンタクトとも呼ばれるゲート電極8と、を含む。
オーミックコンタクト形成工程で、例えばSi3N4層のようなパッシベーション層11を部分的に除去した後、例えばSi3N4層のようなパッシベーション層11の上やバリア層4の上に、TiAlMoAuを堆積することにより、ソースおよびドレインコンタクト7、8が形成される。コンタクト7、8は、続いてアニールされ、オーミック特性が得られる(図11、工程2参照)。この具体例では、ソース及びドレインコンタクト7、8は、トレンチ18中に、トレンチ18の底部まで延びる。ソースおよびドレインコンタクト7、8はバッファ層2と直接接触する。
インターコネクトメタライゼーションスキームが堆積される。
例えばSi3N4層のようなパッシベーション層の上に、第2パッシベーション層12としてSiO2が堆積される(図11、工程3)。
第2パッシベーション層12中に、トレンチ19がエッチングされ、ゲートの占有面積を規定し、ゲートの占有面積の位置でバリア層4(即ち、SiO2第2パッシベーション層12と、同様に例えばSi3N4層のようなその場第1パッシベーション層)を部分的に取り除く。例えば800℃で酸素雰囲気のオーブンに数分入れることにより、試料は酸化工程が行われ、例えばAlNやInAlN層のような第2活性層またはバリア層4が部分的に酸化され(例えば、約0.5nm/分)、バリア層4の残った酸化されない膜厚、換言すればバリア層4の残った部分が、膜厚d1より薄くなり、即ちバッファ層2の膜厚より薄くなる。d2は、キャリア密度が低下し始めるバッファ層の膜厚であり、d1は、2DEGを形成するためのバリア層の臨界膜厚である(図9、10、および図11の工程4参照)。この膜厚において、2DEGは部分的に空乏化し、0ボルトゲートバイアスの最終デバイス10において、ソースおよびドレインコンタクト7、8の間のチャネル中に、電流は流れない。
続いて、ショットキ金属が堆積され、先の工程で形成されるトレンチ18を横切って、リフトオフまたは好適には金属エッチングプロセスによりT型ゲートコンタクト6が形成される(図11、工程5)。
Claims (15)
- 基板(1)上の第1活性層(3)と、
第1活性層(3)の上の第2活性層(4)であって、第2活性層(4)は第1活性層(3)に比較して高いバンドギャップを有し、実質的にGaを含まないで少なくともAlを含み、動作時に、第1活性層(3)と第2活性層(4)の間の界面の少なくとも一部の上に2次元電子ガス(2DEG)層(9)が存在する第2活性層(4)と、
第2活性層(4)の少なくとも一部の上のゲート絶縁層(5)と、
ゲート絶縁層(5)の少なくとも一部の上のゲート電極(6)と、
第2活性層(4)の上のソース電極(7)およびドレイン電極(8)と、を含み、
ゲート絶縁層(5)は第2活性層(4)の少なくとも一部の熱酸化により形成された熱酸化物であり、これにより、第2活性層の上部を消費して第2活性層の厚みを減らし、2DEGを部分的に空乏化した半導体デバイス(10)。 - 第2活性層(4)は、InxAl1−xN(xは0と0.5の間)を含む請求項1に記載の半導体デバイス(10)。
- 第2活性層(4)は、傾斜したインジウム(In)成分、または傾斜したアルミニウム(Al)成分を有し、または第2活性層はインジウム無しである請求項2に記載の半導体デバイス(10)。
- ゲート絶縁層(5)は、少なくともAlおよび酸素を含む請求項1〜3のいずれかに記載の半導体デバイス(10)。
- 第1活性層(3)はIII族窒化物材料を含み、または第1活性層(3)はGaNを含む請求項1〜4のいずれかに記載の半導体デバイス(10)。
- 第2活性層(4)は、更にリセス(19)を含み、ゲート絶縁層(5)が、第2活性層(4)の中のリセス(19)の中に存在する請求項1〜5のいずれかに記載の半導体デバイス(10)。
- 半導体デバイス(10)は、更に、ゲート絶縁層(5)の存在しない第2活性層(4)の少なくとも一部の上にパッシベーション層(11)を含む請求項1〜6のいずれかに記載の半導体デバイス(10)。
- 半導体デバイス(10)は、エンハンスメントモードトランジスタである請求項1〜7のいずれかに記載の半導体デバイス(10)。
- 第3活性層は、基板(1)と第1活性層(3)の間に成長され、第3活性層は、第1活性層のバンドギャップより高いバンドギャップを有し、第3活性層は、第1活性層の焦電分極性より高い焦電分極性を有する請求項1〜8のいずれかに記載の半導体デバイス(10)。
- 半導体デバイス(10)の製造方法であって、
基板(1)の上に第1活性層(3)を提供する工程と、
第1活性層(3)の上に第2活性層(4)を提供する工程であって、第2活性層(4)は第1活性層(3)に比較して高いバンドギャップを有し、実質的にGaを含まないで少なくともAlを含み、動作時に、第1活性層と第2活性層の間の界面の少なくとも一部の上に2次元電子ガス(2DEG)層(9)が存在する工程と、
第2活性層(4)の少なくとも一部を熱酸化により酸化し、ゲート絶縁層(5)を形成する工程と、
ゲート絶縁層(5)の上にゲート電極(6)を提供する工程と、
第2活性層(4)の上にソース電極(7)とドレイン電極(8)を提供する工程と、を含む半導体デバイス(10)の製造方法。 - 第2活性層(4)を提供する工程は、InxAl1−xN(xは0と0.5の間)を含む層を提供する工程で行われ、または第2活性層(4)を提供する工程は、インジウム無しの層を提供する工程で行われる請求項10に記載の製造方法。
- ゲート絶縁層(5)を提供する工程は、少なくともAlと酸素を含む層を提供する工程で行われる請求項10または11に記載の製造方法。
- 第1活性層(3)を提供する工程は、III族窒化物材料を含む層を提供する工程で行われる請求項10〜12のいずれかに記載の製造方法。
- 更に、ゲート絶縁層(5)が存在しない第2活性層(4)の少なくとも一部の上にパッシベーション層(11)を堆積する工程を含む請求項10〜13のいずれかに記載の製造方法。
- 第3活性層は、基板(1)と第1活性層(3)の間に成長され、第3活性層は、第1活性層のバンドギャップより高いバンドギャップを有し、第3活性層は、第1活性層より高い焦電分極性を有する請求項10〜14のいずれかに記載の製造方法。
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US8309987B2 (en) | 2012-11-13 |
EP2146378A3 (en) | 2010-04-28 |
EP2146378B1 (en) | 2019-10-09 |
US20130102140A1 (en) | 2013-04-25 |
US20100012977A1 (en) | 2010-01-21 |
US8809138B2 (en) | 2014-08-19 |
EP2146378A2 (en) | 2010-01-20 |
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