JP2009545838A5 - - Google Patents

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Publication number
JP2009545838A5
JP2009545838A5 JP2009523031A JP2009523031A JP2009545838A5 JP 2009545838 A5 JP2009545838 A5 JP 2009545838A5 JP 2009523031 A JP2009523031 A JP 2009523031A JP 2009523031 A JP2009523031 A JP 2009523031A JP 2009545838 A5 JP2009545838 A5 JP 2009545838A5
Authority
JP
Japan
Prior art keywords
array
data bus
array block
lines
bit lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009523031A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009545838A (ja
JP5279139B2 (ja
Filing date
Publication date
Priority claimed from US11/461,359 external-priority patent/US7463536B2/en
Priority claimed from US11/461,372 external-priority patent/US7570523B2/en
Application filed filed Critical
Priority claimed from PCT/US2007/074903 external-priority patent/WO2008016950A2/en
Publication of JP2009545838A publication Critical patent/JP2009545838A/ja
Publication of JP2009545838A5 publication Critical patent/JP2009545838A5/ja
Application granted granted Critical
Publication of JP5279139B2 publication Critical patent/JP5279139B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2009523031A 2006-07-31 2007-07-31 メモリアレイブロック選択のための２本のデータバスを組込んだメモリアレイのための方法および装置 Expired - Fee Related JP5279139B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/461,359 2006-07-31
US11/461,359 US7463536B2 (en) 2006-07-31 2006-07-31 Memory array incorporating two data busses for memory array block selection
US11/461,372 US7570523B2 (en) 2006-07-31 2006-07-31 Method for using two data busses for memory array block selection
US11/461,372 2006-07-31
PCT/US2007/074903 WO2008016950A2 (en) 2006-07-31 2007-07-31 Method and apparatus for memory array incorporating two data busses for memory array block selection

Publications (3)

Publication Number Publication Date
JP2009545838A JP2009545838A (ja) 2009-12-24
JP2009545838A5 true JP2009545838A5 (enExample) 2010-09-16
JP5279139B2 JP5279139B2 (ja) 2013-09-04

Family

ID=38997823

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009523031A Expired - Fee Related JP5279139B2 (ja) 2006-07-31 2007-07-31 メモリアレイブロック選択のための２本のデータバスを組込んだメモリアレイのための方法および装置

Country Status (5)

Country Link
EP (1) EP2062264B1 (enExample)
JP (1) JP5279139B2 (enExample)
KR (1) KR101494333B1 (enExample)
TW (1) TWI345791B (enExample)
WO (1) WO2008016950A2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2685213C (en) * 2007-05-04 2017-02-21 Technophage, Investigacao E Desenvolvimento Em Biotecnologia, Sa Engineered rabbit antibody variable domains and uses thereof
JP2010218664A (ja) 2009-03-18 2010-09-30 Toshiba Corp 半導体記憶装置およびその制御方法
IT201900001947A1 (it) * 2019-02-11 2020-08-11 Sk Hynix Inc Struttura di decodificatore per una architettura di memoria

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) * 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
JP2535911B2 (ja) * 1987-05-29 1996-09-18 日本電気株式会社 半導体メモリ装置
JPH0793002B2 (ja) * 1987-06-04 1995-10-09 日本電気株式会社 メモリ集積回路
JPH0814985B2 (ja) * 1989-06-06 1996-02-14 富士通株式会社 半導体記憶装置
JP3781793B2 (ja) * 1995-01-10 2006-05-31 株式会社ルネサステクノロジ ダイナミック型半導体記憶装置
JPH0973776A (ja) * 1995-09-07 1997-03-18 Mitsubishi Electric Corp 同期型半導体記憶装置
US6603683B2 (en) * 2001-06-25 2003-08-05 International Business Machines Corporation Decoding scheme for a stacked bank architecture
JP2003077276A (ja) * 2001-08-31 2003-03-14 Nec Corp 半導体メモリ
KR100481857B1 (ko) * 2002-08-14 2005-04-11 삼성전자주식회사 레이아웃 면적을 줄이고 뱅크 마다 독립적인 동작을수행할 수 있는 디코더를 갖는 플레쉬 메모리 장치
US7233024B2 (en) * 2003-03-31 2007-06-19 Sandisk 3D Llc Three-dimensional memory device incorporating segmented bit line memory array
JP2005025805A (ja) * 2003-06-30 2005-01-27 Renesas Technology Corp 半導体記憶装置

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