JP2010010369A5 - - Google Patents

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Publication number
JP2010010369A5
JP2010010369A5 JP2008167606A JP2008167606A JP2010010369A5 JP 2010010369 A5 JP2010010369 A5 JP 2010010369A5 JP 2008167606 A JP2008167606 A JP 2008167606A JP 2008167606 A JP2008167606 A JP 2008167606A JP 2010010369 A5 JP2010010369 A5 JP 2010010369A5
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JP
Japan
Prior art keywords
bit line
transistor
cell
memory
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2008167606A
Other languages
English (en)
Japanese (ja)
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JP2010010369A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2008167606A priority Critical patent/JP2010010369A/ja
Priority claimed from JP2008167606A external-priority patent/JP2010010369A/ja
Priority to US12/485,253 priority patent/US8081525B2/en
Publication of JP2010010369A publication Critical patent/JP2010010369A/ja
Publication of JP2010010369A5 publication Critical patent/JP2010010369A5/ja
Withdrawn legal-status Critical Current

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JP2008167606A 2008-06-26 2008-06-26 混載メモリ装置及び半導体装置 Withdrawn JP2010010369A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008167606A JP2010010369A (ja) 2008-06-26 2008-06-26 混載メモリ装置及び半導体装置
US12/485,253 US8081525B2 (en) 2008-06-26 2009-06-16 Memory device including combination SRAM-ROM cells and SRAM cells alternately arranged and semiconductor device including the memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008167606A JP2010010369A (ja) 2008-06-26 2008-06-26 混載メモリ装置及び半導体装置

Publications (2)

Publication Number Publication Date
JP2010010369A JP2010010369A (ja) 2010-01-14
JP2010010369A5 true JP2010010369A5 (enExample) 2011-05-06

Family

ID=41447227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008167606A Withdrawn JP2010010369A (ja) 2008-06-26 2008-06-26 混載メモリ装置及び半導体装置

Country Status (2)

Country Link
US (1) US8081525B2 (enExample)
JP (1) JP2010010369A (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010288334A (ja) * 2009-06-09 2010-12-24 Panasonic Corp スイッチング電源装置及び半導体装置
US9691495B2 (en) * 2014-07-30 2017-06-27 Nxp Usa, Inc. Memory array with RAM and embedded ROM
GB2543528B (en) * 2015-10-20 2020-01-15 Advanced Risc Mach Ltd Memory circuit
JP7065007B2 (ja) * 2018-10-01 2022-05-11 ルネサスエレクトロニクス株式会社 半導体装置
US11069424B2 (en) * 2018-11-07 2021-07-20 Arm Limited Sensor for performance variation of memory read and write characteristics

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2515706B2 (ja) 1986-08-22 1996-07-10 株式会社日立マイコンシステム マイクロコンピュ―タ
US4922441A (en) * 1987-01-19 1990-05-01 Ricoh Company, Ltd. Gate array device having a memory cell/interconnection region
US5027319A (en) * 1988-09-02 1991-06-25 Motorola, Inc. Gate array macro cell
JPH0834059B2 (ja) * 1990-08-31 1996-03-29 三菱電機株式会社 半導体記憶装置
JP3273068B2 (ja) * 1992-04-30 2002-04-08 シャープ株式会社 システムメモリ及び該メモリを内蔵したマイクロコンピュータ
JP2899175B2 (ja) * 1992-07-03 1999-06-02 シャープ株式会社 半導体記憶装置
US5528534A (en) 1995-03-21 1996-06-18 At&T Corp. High-density read-only memory employing multiple bit-line interconnection
US5923582A (en) 1997-06-03 1999-07-13 Cypress Semiconductor Corp. SRAM with ROM functionality
US5870326A (en) 1997-08-12 1999-02-09 Intel Corporation Information encoding by multiple line selection
US6002607A (en) 1998-02-24 1999-12-14 National Semiconductor Corporation Read-only-memory (ROM) having a memory cell that stores a plurality of bits of information
US6041008A (en) 1998-05-13 2000-03-21 Micron Technology Inc. Method and apparatus for embedded read only memory in static random access memory
KR100295666B1 (ko) * 1998-10-28 2001-08-07 김영환 혼성메모리장치
KR100313514B1 (ko) 1999-05-11 2001-11-17 김영환 하이브리드 메모리 장치
TWI249165B (en) 2002-07-02 2006-02-11 Brilliance Semiconductor Inc Memory cell combining static random access memory with mask read only memory
GB0406038D0 (en) 2004-03-17 2004-04-21 Cambridge Silicon Radio Ltd Method for reading rom cell
US7301828B2 (en) 2006-02-27 2007-11-27 Agere Systems Inc. Decoding techniques for read-only memory
US7324364B2 (en) 2006-02-27 2008-01-29 Agere Systems Inc. Layout techniques for memory circuitry

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