JP4956087B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP4956087B2 JP4956087B2 JP2006214951A JP2006214951A JP4956087B2 JP 4956087 B2 JP4956087 B2 JP 4956087B2 JP 2006214951 A JP2006214951 A JP 2006214951A JP 2006214951 A JP2006214951 A JP 2006214951A JP 4956087 B2 JP4956087 B2 JP 4956087B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
Description
メモリセルアレイブロックA1、A2により、1つのメモリセルアレイ1が形成される。領域Bは、従来において配線を引き回すための領域として用いられていた周辺領域であり、本実施の形態では利用されない。また、領域Cは、後述する読出し回路12を含む周辺回路が形成される周辺回路領域である。なお、領域Dは、配線引き回し等を行うスペースが無い狭い周辺領域である。
この実施の形態の半導体記憶装置は、メモリセルアレイブロックA1、A2を備えた図1と同様のメモリセルアレイ1をX軸方向に2個並べて配置する構成を有している。1つのメモリセルアレイ1にそれぞれ16個、計32個(16×2)の読出し回路12が設けられている。その他は、各メモリセルアレイ1の領域の境界においてデータ入出力線I/Oが分割されている点なども含め、第1の実施の形態と同様である。すなわち、1つのメモリセルアレイ1において16ビット同時読出しが可能であるため、2つのメモリセルアレイ1により16ビットのインターリーブアクセスを実現することが可能になる。
Claims (6)
- メモリセルアレイ領域に配置され第1方向に沿って延びる複数のワード線と前記第1方向と直交する第2方向に沿って延びる複数のビット線の交点に複数のメモリセルを構成してなるメモリセルアレイブロックと、
データキャッシュアレイ領域に配置され前記メモリセルから読み出されたデータを一時保持するデータキャッシュを配列してなるデータキャッシュアレイと、
前記メモリセルアレイブロック中に前記複数のビット線ごとに前記第2方向に延びる様に前記第1方向に所定の間隔で形成され前記ワード線又はこれと同一方向に配線された信号線と他の金属配線とを接続するコンタクトが形成される複数のシャント領域と、
前記データキャッシュアレイ領域中の前記シャント領域の前記第2方向の延長線上に形成され、前記データキャッシュが形成されていない領域である延長領域と、
前記延長領域内に前記第2方向に沿って形成される引出し線と、
前記第1方向に沿って延びるように形成され同時に選択され得る複数の前記ビット線のデータを前記データキャッシュアレイを介して同時に転送可能に配置された複数のデータ入出力線と、
前記データキャッシュアレイの周囲に配置され前記複数のデータ入出力線がそれぞれ接続される複数の読出回路と
を備え、
前記複数のデータ入出力線は、前記引出し線と前記延長領域において接続され、前記引出し線を介して前記読出し回路と接続される
ことを特徴とする半導体記憶装置。 - 複数の前記メモリセルアレイブロックによりメモリセルアレイが構成され、
前記データ入出力線は、複数の前記メモリセルアレイブロックの境界位置において分割されていることを特徴とする請求項1記載の半導体記憶装置。 - 前記メモリセルアレイブロックが第1方向に沿って複数個並べて配置され、読出し回路は、複数個の前記メモリセルアレイブロックに対しインターリーブアクセスを実行可能に構成されたことを特徴とする請求項1記載の半導体記憶装置。
- 前記データ入出力線は、
前記ビット線の1つのデータが転送される第1のデータ入出力線と、
前記ビット線の1つのデータと対をなす相補ビット線のデータが転送される第2のデータ入出力線とを備え、
前記引出し線は、前記第1のデータ入出力線と接続される第1の引出し線と、前記第2のデータ入出力線と接続される第2の引出し線と
を備えたことを特徴とする請求項1記載の半導体記憶装置。 - 前記延長領域に沿って、前記データキャッシュを構成する半導体素子に一定の信号を供給する信号線を配置してなることを特徴とする請求項1記載の半導体記憶装置。
- 前記延長領域は、前記引出し線のみが形成された空き領域であることを特徴とする請求項1乃至5のいずれか記載の半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006214951A JP4956087B2 (ja) | 2006-08-07 | 2006-08-07 | 半導体記憶装置 |
KR1020070077993A KR100899466B1 (ko) | 2006-08-07 | 2007-08-03 | 반도체 기억 장치 |
US11/834,932 US7649761B2 (en) | 2006-08-07 | 2007-08-07 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006214951A JP4956087B2 (ja) | 2006-08-07 | 2006-08-07 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008041967A JP2008041967A (ja) | 2008-02-21 |
JP4956087B2 true JP4956087B2 (ja) | 2012-06-20 |
Family
ID=39176645
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006214951A Active JP4956087B2 (ja) | 2006-08-07 | 2006-08-07 | 半導体記憶装置 |
Country Status (3)
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US (1) | US7649761B2 (ja) |
JP (1) | JP4956087B2 (ja) |
KR (1) | KR100899466B1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100945796B1 (ko) * | 2008-05-08 | 2010-03-08 | 주식회사 하이닉스반도체 | 반도체 집적 회로 |
JP5197406B2 (ja) * | 2009-01-27 | 2013-05-15 | 株式会社東芝 | 半導体記憶装置 |
US10474581B2 (en) * | 2016-03-25 | 2019-11-12 | Micron Technology, Inc. | Apparatuses and methods for cache operations |
US10049721B1 (en) | 2017-03-27 | 2018-08-14 | Micron Technology, Inc. | Apparatuses and methods for in-memory operations |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4996378A (en) * | 1989-07-13 | 1991-02-26 | Atochem North America, Inc. | Process for production of 1,1-dichloro-1-fluoroethane and/or 1-chloro-1,1-difluoroethane |
US5652723A (en) * | 1991-04-18 | 1997-07-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device |
JP3476231B2 (ja) * | 1993-01-29 | 2003-12-10 | 三菱電機エンジニアリング株式会社 | 同期型半導体記憶装置および半導体記憶装置 |
JP3364810B2 (ja) * | 1993-09-14 | 2003-01-08 | 三菱電機株式会社 | 半導体記憶装置 |
JP3725911B2 (ja) * | 1994-06-02 | 2005-12-14 | 株式会社ルネサステクノロジ | 半導体装置 |
US6084816A (en) * | 1998-04-16 | 2000-07-04 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US6314042B1 (en) * | 1998-05-22 | 2001-11-06 | Mitsubishi Denki Kabushiki Kaisha | Fast accessible semiconductor memory device |
JP2000150820A (ja) | 1998-11-09 | 2000-05-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6249451B1 (en) * | 1999-02-08 | 2001-06-19 | Kabushiki Kaisha Toshiba | Data line connections with twisting scheme technical field |
JP2002319634A (ja) * | 2001-04-23 | 2002-10-31 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2003168287A (ja) | 2001-07-24 | 2003-06-13 | Toshiba Corp | メモリモジュール、メモリシステム、および、データ転送方法 |
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2006
- 2006-08-07 JP JP2006214951A patent/JP4956087B2/ja active Active
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2007
- 2007-08-03 KR KR1020070077993A patent/KR100899466B1/ko active IP Right Grant
- 2007-08-07 US US11/834,932 patent/US7649761B2/en active Active
Also Published As
Publication number | Publication date |
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KR100899466B1 (ko) | 2009-05-27 |
JP2008041967A (ja) | 2008-02-21 |
KR20080013743A (ko) | 2008-02-13 |
US7649761B2 (en) | 2010-01-19 |
US20080285324A1 (en) | 2008-11-20 |
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