TWI345791B - Method and apparatus for memory array incorporating two data busses for memory array block selection - Google Patents
Method and apparatus for memory array incorporating two data busses for memory array block selection Download PDFInfo
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- TWI345791B TWI345791B TW096128052A TW96128052A TWI345791B TW I345791 B TWI345791 B TW I345791B TW 096128052 A TW096128052 A TW 096128052A TW 96128052 A TW96128052 A TW 96128052A TW I345791 B TWI345791 B TW I345791B
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Links
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- 238000000034 method Methods 0.000 title claims description 76
- 230000002441 reversible effect Effects 0.000 claims description 81
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- 238000005859 coupling reaction Methods 0.000 claims description 44
- 238000003491 array Methods 0.000 claims description 23
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/461,359 US7463536B2 (en) | 2006-07-31 | 2006-07-31 | Memory array incorporating two data busses for memory array block selection |
| US11/461,372 US7570523B2 (en) | 2006-07-31 | 2006-07-31 | Method for using two data busses for memory array block selection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200828340A TW200828340A (en) | 2008-07-01 |
| TWI345791B true TWI345791B (en) | 2011-07-21 |
Family
ID=38997823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW096128052A TWI345791B (en) | 2006-07-31 | 2007-07-31 | Method and apparatus for memory array incorporating two data busses for memory array block selection |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP2062264B1 (enExample) |
| JP (1) | JP5279139B2 (enExample) |
| KR (1) | KR101494333B1 (enExample) |
| TW (1) | TWI345791B (enExample) |
| WO (1) | WO2008016950A2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2685213C (en) * | 2007-05-04 | 2017-02-21 | Technophage, Investigacao E Desenvolvimento Em Biotecnologia, Sa | Engineered rabbit antibody variable domains and uses thereof |
| JP2010218664A (ja) | 2009-03-18 | 2010-09-30 | Toshiba Corp | 半導体記憶装置およびその制御方法 |
| IT201900001947A1 (it) * | 2019-02-11 | 2020-08-11 | Sk Hynix Inc | Struttura di decodificatore per una architettura di memoria |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960003526B1 (ko) * | 1992-10-02 | 1996-03-14 | 삼성전자주식회사 | 반도체 메모리장치 |
| JP2535911B2 (ja) * | 1987-05-29 | 1996-09-18 | 日本電気株式会社 | 半導体メモリ装置 |
| JPH0793002B2 (ja) * | 1987-06-04 | 1995-10-09 | 日本電気株式会社 | メモリ集積回路 |
| JPH0814985B2 (ja) * | 1989-06-06 | 1996-02-14 | 富士通株式会社 | 半導体記憶装置 |
| JP3781793B2 (ja) * | 1995-01-10 | 2006-05-31 | 株式会社ルネサステクノロジ | ダイナミック型半導体記憶装置 |
| JPH0973776A (ja) * | 1995-09-07 | 1997-03-18 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
| US6603683B2 (en) * | 2001-06-25 | 2003-08-05 | International Business Machines Corporation | Decoding scheme for a stacked bank architecture |
| JP2003077276A (ja) * | 2001-08-31 | 2003-03-14 | Nec Corp | 半導体メモリ |
| KR100481857B1 (ko) * | 2002-08-14 | 2005-04-11 | 삼성전자주식회사 | 레이아웃 면적을 줄이고 뱅크 마다 독립적인 동작을수행할 수 있는 디코더를 갖는 플레쉬 메모리 장치 |
| US7233024B2 (en) * | 2003-03-31 | 2007-06-19 | Sandisk 3D Llc | Three-dimensional memory device incorporating segmented bit line memory array |
| JP2005025805A (ja) * | 2003-06-30 | 2005-01-27 | Renesas Technology Corp | 半導体記憶装置 |
-
2007
- 2007-07-31 TW TW096128052A patent/TWI345791B/zh not_active IP Right Cessation
- 2007-07-31 EP EP07840623.8A patent/EP2062264B1/en not_active Not-in-force
- 2007-07-31 WO PCT/US2007/074903 patent/WO2008016950A2/en not_active Ceased
- 2007-07-31 JP JP2009523031A patent/JP5279139B2/ja not_active Expired - Fee Related
- 2007-07-31 KR KR1020097004228A patent/KR101494333B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| TW200828340A (en) | 2008-07-01 |
| JP2009545838A (ja) | 2009-12-24 |
| KR20090057374A (ko) | 2009-06-05 |
| WO2008016950A3 (en) | 2008-05-02 |
| JP5279139B2 (ja) | 2013-09-04 |
| WO2008016950A2 (en) | 2008-02-07 |
| KR101494333B1 (ko) | 2015-02-17 |
| EP2062264A4 (en) | 2010-11-10 |
| EP2062264A2 (en) | 2009-05-27 |
| EP2062264B1 (en) | 2015-10-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |