KR101494333B1 - 메모리 어레이 블록 선택을 위하여 두 개의 데이터 버스를 통합한 메모리 어레이용 방법과 장치 - Google Patents

메모리 어레이 블록 선택을 위하여 두 개의 데이터 버스를 통합한 메모리 어레이용 방법과 장치 Download PDF

Info

Publication number
KR101494333B1
KR101494333B1 KR1020097004228A KR20097004228A KR101494333B1 KR 101494333 B1 KR101494333 B1 KR 101494333B1 KR 1020097004228 A KR1020097004228 A KR 1020097004228A KR 20097004228 A KR20097004228 A KR 20097004228A KR 101494333 B1 KR101494333 B1 KR 101494333B1
Authority
KR
South Korea
Prior art keywords
array
lines
blocks
word line
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020097004228A
Other languages
English (en)
Korean (ko)
Other versions
KR20090057374A (ko
Inventor
로이 이. 쉐얼라인
루카 쥐. 파솔리
크리스토퍼 제이. 페티
Original Assignee
쌘디스크 3디 엘엘씨
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/461,359 external-priority patent/US7463536B2/en
Priority claimed from US11/461,372 external-priority patent/US7570523B2/en
Application filed by 쌘디스크 3디 엘엘씨 filed Critical 쌘디스크 3디 엘엘씨
Publication of KR20090057374A publication Critical patent/KR20090057374A/ko
Application granted granted Critical
Publication of KR101494333B1 publication Critical patent/KR101494333B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
KR1020097004228A 2006-07-31 2007-07-31 메모리 어레이 블록 선택을 위하여 두 개의 데이터 버스를 통합한 메모리 어레이용 방법과 장치 Expired - Fee Related KR101494333B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/461,359 2006-07-31
US11/461,359 US7463536B2 (en) 2006-07-31 2006-07-31 Memory array incorporating two data busses for memory array block selection
US11/461,372 US7570523B2 (en) 2006-07-31 2006-07-31 Method for using two data busses for memory array block selection
US11/461,372 2006-07-31
PCT/US2007/074903 WO2008016950A2 (en) 2006-07-31 2007-07-31 Method and apparatus for memory array incorporating two data busses for memory array block selection

Publications (2)

Publication Number Publication Date
KR20090057374A KR20090057374A (ko) 2009-06-05
KR101494333B1 true KR101494333B1 (ko) 2015-02-17

Family

ID=38997823

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020097004228A Expired - Fee Related KR101494333B1 (ko) 2006-07-31 2007-07-31 메모리 어레이 블록 선택을 위하여 두 개의 데이터 버스를 통합한 메모리 어레이용 방법과 장치

Country Status (5)

Country Link
EP (1) EP2062264B1 (enExample)
JP (1) JP5279139B2 (enExample)
KR (1) KR101494333B1 (enExample)
TW (1) TWI345791B (enExample)
WO (1) WO2008016950A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12507416B2 (en) 2020-10-22 2025-12-23 Samsung Electronics Co., Ltd. Memory device including memory blocks different from each other

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2685213C (en) * 2007-05-04 2017-02-21 Technophage, Investigacao E Desenvolvimento Em Biotecnologia, Sa Engineered rabbit antibody variable domains and uses thereof
JP2010218664A (ja) 2009-03-18 2010-09-30 Toshiba Corp 半導体記憶装置およびその制御方法
IT201900001947A1 (it) * 2019-02-11 2020-08-11 Sk Hynix Inc Struttura di decodificatore per una architettura di memoria

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831924A (en) * 1995-09-07 1998-11-03 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device having a plurality of banks distributed in a plurality of memory arrays
US20040188714A1 (en) * 2003-03-31 2004-09-30 Scheuerlein Roy E. Three-dimensional memory device incorporating segmented bit line memory array

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) * 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
JP2535911B2 (ja) * 1987-05-29 1996-09-18 日本電気株式会社 半導体メモリ装置
JPH0793002B2 (ja) * 1987-06-04 1995-10-09 日本電気株式会社 メモリ集積回路
JPH0814985B2 (ja) * 1989-06-06 1996-02-14 富士通株式会社 半導体記憶装置
JP3781793B2 (ja) * 1995-01-10 2006-05-31 株式会社ルネサステクノロジ ダイナミック型半導体記憶装置
US6603683B2 (en) * 2001-06-25 2003-08-05 International Business Machines Corporation Decoding scheme for a stacked bank architecture
JP2003077276A (ja) * 2001-08-31 2003-03-14 Nec Corp 半導体メモリ
KR100481857B1 (ko) * 2002-08-14 2005-04-11 삼성전자주식회사 레이아웃 면적을 줄이고 뱅크 마다 독립적인 동작을수행할 수 있는 디코더를 갖는 플레쉬 메모리 장치
JP2005025805A (ja) * 2003-06-30 2005-01-27 Renesas Technology Corp 半導体記憶装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831924A (en) * 1995-09-07 1998-11-03 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device having a plurality of banks distributed in a plurality of memory arrays
US20040188714A1 (en) * 2003-03-31 2004-09-30 Scheuerlein Roy E. Three-dimensional memory device incorporating segmented bit line memory array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12507416B2 (en) 2020-10-22 2025-12-23 Samsung Electronics Co., Ltd. Memory device including memory blocks different from each other

Also Published As

Publication number Publication date
TW200828340A (en) 2008-07-01
JP2009545838A (ja) 2009-12-24
KR20090057374A (ko) 2009-06-05
TWI345791B (en) 2011-07-21
WO2008016950A3 (en) 2008-05-02
JP5279139B2 (ja) 2013-09-04
WO2008016950A2 (en) 2008-02-07
EP2062264A4 (en) 2010-11-10
EP2062264A2 (en) 2009-05-27
EP2062264B1 (en) 2015-10-07

Similar Documents

Publication Publication Date Title
US8509025B2 (en) Memory array circuit incorporating multiple array block selection and related method
US7463546B2 (en) Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders
CN101506896B (zh) 用于并入有用于存储器阵列区块选择的两个数据总线的存储器阵列的方法和设备
US7554832B2 (en) Passive element memory array incorporating reversible polarity word line and bit line decoders
CN101506897B (zh) 用于将读取/写入电路耦合到存储器阵列的双数据相依总线
US7570523B2 (en) Method for using two data busses for memory array block selection
JP2013539152A (ja) メモリアレイの動作に順方向モードおよび逆方向モードをもたらすデコーダ回路、ならびにこれにバイアスを加える方法
US7633828B2 (en) Hierarchical bit line bias bus for block selectable memory array
US7596050B2 (en) Method for using a hierarchical bit line bias bus for block selectable memory array
KR101478193B1 (ko) 가역 극성 워드 라인과 비트 라인 디코더를 결합한 패시브 엘리먼트 메모리 어레이용 방법과 장치
KR101465557B1 (ko) 메모리 어레이에 판독/기입 회로를 결합하기 위한 듀얼 데이터 종속 버스
KR101494333B1 (ko) 메모리 어레이 블록 선택을 위하여 두 개의 데이터 버스를 통합한 메모리 어레이용 방법과 장치
WO2008016951A2 (en) Method and apparatus for hierarchical bit line bias bus for block selectable memory array

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R17-X000 Change to representative recorded

St.27 status event code: A-5-5-R10-R17-oth-X000

FPAY Annual fee payment

Payment date: 20180118

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20190116

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20200115

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20230212

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20230212