JP2007250092A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2007250092A5 JP2007250092A5 JP2006072899A JP2006072899A JP2007250092A5 JP 2007250092 A5 JP2007250092 A5 JP 2007250092A5 JP 2006072899 A JP2006072899 A JP 2006072899A JP 2006072899 A JP2006072899 A JP 2006072899A JP 2007250092 A5 JP2007250092 A5 JP 2007250092A5
- Authority
- JP
- Japan
- Prior art keywords
- bit line
- memory cell
- selection circuit
- line
- cell array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 9
- 239000011159 matrix material Substances 0.000 claims 7
- 230000004044 response Effects 0.000 claims 6
- 230000003213 activating effect Effects 0.000 claims 4
- 238000003491 array Methods 0.000 claims 2
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006072899A JP4805700B2 (ja) | 2006-03-16 | 2006-03-16 | 半導体記憶装置 |
| US11/686,892 US7639559B2 (en) | 2006-03-16 | 2007-03-15 | Semiconductor memory device |
| CNA2007100886135A CN101038791A (zh) | 2006-03-16 | 2007-03-16 | 半导体存储装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006072899A JP4805700B2 (ja) | 2006-03-16 | 2006-03-16 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007250092A JP2007250092A (ja) | 2007-09-27 |
| JP2007250092A5 true JP2007250092A5 (enExample) | 2009-03-19 |
| JP4805700B2 JP4805700B2 (ja) | 2011-11-02 |
Family
ID=38517645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006072899A Expired - Fee Related JP4805700B2 (ja) | 2006-03-16 | 2006-03-16 | 半導体記憶装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7639559B2 (enExample) |
| JP (1) | JP4805700B2 (enExample) |
| CN (1) | CN101038791A (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5343916B2 (ja) | 2010-04-16 | 2013-11-13 | 富士通セミコンダクター株式会社 | 半導体メモリ |
| CN103106925B (zh) * | 2013-01-04 | 2016-07-06 | 苏州兆芯半导体科技有限公司 | 串联rom单元及其读取方法 |
| TW201521026A (zh) * | 2013-11-18 | 2015-06-01 | Faraday Tech Corp | 非揮發性記憶體 |
| JP2016170833A (ja) * | 2015-03-12 | 2016-09-23 | 株式会社東芝 | 半導体装置 |
| US9899069B1 (en) * | 2016-07-29 | 2018-02-20 | Nxp Usa, Inc. | Adaptable sense circuitry and method for read-only memory |
| US10777255B2 (en) * | 2018-03-19 | 2020-09-15 | Samsung Electronics Co., Ltd. | Control signal generator for sense amplifier and memory device including the control signal generator |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0836895A (ja) | 1994-07-26 | 1996-02-06 | Hitachi Ltd | 半導体集積回路装置 |
| JPH09231783A (ja) | 1996-02-26 | 1997-09-05 | Sharp Corp | 半導体記憶装置 |
| KR100240418B1 (ko) | 1996-12-31 | 2000-03-02 | 윤종용 | 반도체 독출 전용 메모리 및 그의 독출 방법 |
| JP2004247026A (ja) * | 2003-01-24 | 2004-09-02 | Renesas Technology Corp | 半導体集積回路及びicカード |
| JP2005183533A (ja) * | 2003-12-17 | 2005-07-07 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| JP2006146982A (ja) * | 2004-11-16 | 2006-06-08 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| JP2007035169A (ja) * | 2005-07-27 | 2007-02-08 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
-
2006
- 2006-03-16 JP JP2006072899A patent/JP4805700B2/ja not_active Expired - Fee Related
-
2007
- 2007-03-15 US US11/686,892 patent/US7639559B2/en active Active
- 2007-03-16 CN CNA2007100886135A patent/CN101038791A/zh active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10242728B2 (en) | DPU architecture | |
| US10180808B2 (en) | Software stack and programming for DPU operations | |
| JP2009545095A5 (enExample) | ||
| JP2012252765A5 (ja) | 半導体装置 | |
| CN108022615B (zh) | 动态随机存取存储器处理单元 | |
| TW200739587A (en) | Nonvolatile semiconductor memory device | |
| JP2010009674A5 (enExample) | ||
| EP1460638A3 (en) | Semiconductor memory device with shift register-based refresh address generation circuit | |
| ATE511144T1 (de) | Mikro-tile-speicherschnittstelle | |
| TW201129985A (en) | Non-volatile memory array architecture incorporating 1T-1R near 4F2 memory cell | |
| JP2004517504A5 (enExample) | ||
| JP2012216266A (ja) | 半導体記憶装置 | |
| JP2012195051A5 (enExample) | ||
| WO2012088137A3 (en) | Memory array having local source lines | |
| JP2006508481A5 (enExample) | ||
| EP2888740B1 (en) | Apparatuses and methods involving accessing distributed sub-blocks of memory cells | |
| US8050102B2 (en) | Word line activation in memory devices | |
| KR20150028727A (ko) | 공유 판독 및 기록 회로들을 가진 타일들을 포함하는 메모리 장치 | |
| JP2015529929A5 (enExample) | ||
| JP2007250092A5 (enExample) | ||
| JP2015518230A5 (enExample) | ||
| JP2006127741A5 (enExample) | ||
| US10468081B2 (en) | Semiconductor storage device | |
| JP2011060402A5 (enExample) | ||
| DE60100581D1 (de) | Dynamischer Speicher mit redundanten Zellen |