JP2009540606A5 - - Google Patents

Download PDF

Info

Publication number
JP2009540606A5
JP2009540606A5 JP2009515464A JP2009515464A JP2009540606A5 JP 2009540606 A5 JP2009540606 A5 JP 2009540606A5 JP 2009515464 A JP2009515464 A JP 2009515464A JP 2009515464 A JP2009515464 A JP 2009515464A JP 2009540606 A5 JP2009540606 A5 JP 2009540606A5
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit die
electrical contact
wirebond
electrically coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009515464A
Other languages
English (en)
Japanese (ja)
Other versions
JP5320611B2 (ja
JP2009540606A (ja
Filing date
Publication date
Priority claimed from US11/801,317 external-priority patent/US7535110B2/en
Application filed filed Critical
Publication of JP2009540606A publication Critical patent/JP2009540606A/ja
Publication of JP2009540606A5 publication Critical patent/JP2009540606A5/ja
Application granted granted Critical
Publication of JP5320611B2 publication Critical patent/JP5320611B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2009515464A 2006-06-15 2007-06-13 スタックダイパッケージ Active JP5320611B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US81377806P 2006-06-15 2006-06-15
US60/813,778 2006-06-15
US11/801,317 2007-05-09
US11/801,317 US7535110B2 (en) 2006-06-15 2007-05-09 Stack die packages
PCT/US2007/013821 WO2007146307A2 (en) 2006-06-15 2007-06-13 Stack die packages

Publications (3)

Publication Number Publication Date
JP2009540606A JP2009540606A (ja) 2009-11-19
JP2009540606A5 true JP2009540606A5 (enExample) 2010-07-22
JP5320611B2 JP5320611B2 (ja) 2013-10-23

Family

ID=38666964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009515464A Active JP5320611B2 (ja) 2006-06-15 2007-06-13 スタックダイパッケージ

Country Status (6)

Country Link
US (2) US7535110B2 (enExample)
EP (1) EP2033220B1 (enExample)
JP (1) JP5320611B2 (enExample)
CN (1) CN101506975B (enExample)
TW (1) TWI429050B (enExample)
WO (1) WO2007146307A2 (enExample)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5388422B2 (ja) * 2007-05-11 2014-01-15 スパンション エルエルシー 半導体装置及びその製造方法
US7677109B2 (en) * 2008-02-27 2010-03-16 Honeywell International Inc. Pressure sense die pad layout and method for direct wire bonding to programmable compensation integrated circuit die
US8310051B2 (en) 2008-05-27 2012-11-13 Mediatek Inc. Package-on-package with fan-out WLCSP
US8093722B2 (en) * 2008-05-27 2012-01-10 Mediatek Inc. System-in-package with fan-out WLCSP
US8896126B2 (en) 2011-08-23 2014-11-25 Marvell World Trade Ltd. Packaging DRAM and SOC in an IC package
US8253231B2 (en) 2008-09-23 2012-08-28 Marvell International Ltd. Stacked integrated circuit package using a window substrate
US9009393B1 (en) 2008-09-23 2015-04-14 Marvell International Ltd. Hybrid solid-state disk (SSD)/hard disk drive (HDD) architectures
US20100213588A1 (en) * 2009-02-20 2010-08-26 Tung-Hsien Hsieh Wire bond chip package
US8236607B2 (en) * 2009-06-19 2012-08-07 Stats Chippac Ltd. Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof
US8304917B2 (en) * 2009-12-03 2012-11-06 Powertech Technology Inc. Multi-chip stacked package and its mother chip to save interposer
TWI501380B (zh) * 2010-01-29 2015-09-21 Nat Chip Implementation Ct Nat Applied Res Lab 多基板晶片模組堆疊之三維系統晶片結構
KR101683814B1 (ko) 2010-07-26 2016-12-08 삼성전자주식회사 관통 전극을 구비하는 반도체 장치
US9490003B2 (en) * 2011-03-31 2016-11-08 Intel Corporation Induced thermal gradients
US9658678B2 (en) 2011-03-31 2017-05-23 Intel Corporation Induced thermal gradients
US8674483B2 (en) 2011-06-27 2014-03-18 Marvell World Trade Ltd. Methods and arrangements relating to semiconductor packages including multi-memory dies
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
KR101894823B1 (ko) 2011-10-03 2018-09-04 인벤사스 코포레이션 평행한 윈도우를 갖는 다중-다이 와이어 본드 어셈블리를 위한 스터브 최소화
US8513813B2 (en) 2011-10-03 2013-08-20 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
KR20140085497A (ko) 2011-10-03 2014-07-07 인벤사스 코포레이션 직교 윈도가 있는 멀티-다이 와이어본드 어셈블리를 위한 스터브 최소화
US8659142B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8917532B2 (en) 2011-10-03 2014-12-23 Invensas Corporation Stub minimization with terminal grids offset from center of package
US8436457B2 (en) 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8610260B2 (en) 2011-10-03 2013-12-17 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
US8659139B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US8441111B2 (en) 2011-10-03 2013-05-14 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
CN102446882B (zh) * 2011-12-30 2013-12-04 北京工业大学 一种半导体封装中封装系统结构及制造方法
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
CN103426871B (zh) * 2013-07-25 2017-05-31 上海航天测控通信研究所 一种高密度混合叠层封装结构及其制作方法
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
CN103558903A (zh) * 2013-11-12 2014-02-05 上海航天测控通信研究所 一种具有抗辐性能的PowerPC计算机模块
US9153560B2 (en) 2014-01-22 2015-10-06 Qualcomm Incorporated Package on package (PoP) integrated device comprising a redistribution layer
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
JP2016192447A (ja) * 2015-03-30 2016-11-10 株式会社東芝 半導体装置
BR112017018820A2 (pt) * 2015-04-14 2018-04-24 Huawei Technologies Co., Ltd. chip
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
US9953904B1 (en) 2016-10-25 2018-04-24 Nxp Usa, Inc. Electronic component package with heatsink and multiple electronic components
CN108336030A (zh) * 2018-01-16 2018-07-27 奥肯思（北京）科技有限公司 一种多层堆叠系统级封装
KR102699633B1 (ko) 2019-06-25 2024-08-29 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11075147B2 (en) * 2019-07-08 2021-07-27 Texas Instruments Incorporated Stacked die semiconductor package
CN110943077A (zh) * 2019-11-08 2020-03-31 关键禾芯科技股份有限公司 毫米波应用的多颗晶片封装结构
US20240072002A1 (en) * 2022-08-23 2024-02-29 Micron Technology, Inc. Semiconductor devices, assemblies, and associated methods

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0274046A (ja) * 1988-09-09 1990-03-14 Nec Ic Microcomput Syst Ltd 半導体集積回路装置
JP3602888B2 (ja) * 1995-06-14 2004-12-15 松下電器産業株式会社 半導体装置
US5815372A (en) * 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US6271598B1 (en) * 1997-07-29 2001-08-07 Cubic Memory, Inc. Conductive epoxy flip-chip on chip
JP3111312B2 (ja) * 1997-10-29 2000-11-20 ローム株式会社 半導体装置
US6413797B2 (en) 1997-10-09 2002-07-02 Rohm Co., Ltd. Semiconductor device and method for making the same
US6222260B1 (en) * 1998-05-07 2001-04-24 Vlsi Technology, Inc. Integrated circuit device with integral decoupling capacitor
JP3494901B2 (ja) * 1998-09-18 2004-02-09 シャープ株式会社 半導体集積回路装置
JP2001196529A (ja) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp 半導体装置及びその配線方法
JP2001223324A (ja) * 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
JP2003197856A (ja) * 2001-12-28 2003-07-11 Oki Electric Ind Co Ltd 半導体装置
JP2003332522A (ja) * 2002-05-17 2003-11-21 Mitsubishi Electric Corp 半導体装置
US6747341B2 (en) * 2002-06-27 2004-06-08 Semiconductor Components Industries, L.L.C. Integrated circuit and laminated leadframe package
JP2005109068A (ja) * 2003-09-30 2005-04-21 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP4103796B2 (ja) * 2003-12-25 2008-06-18 沖電気工業株式会社 半導体チップパッケージ及びマルチチップパッケージ
JP2005268534A (ja) * 2004-03-18 2005-09-29 Shinko Electric Ind Co Ltd 半導体チップおよび積層型半導体装置
US20050212144A1 (en) * 2004-03-25 2005-09-29 Rugg William L Stacked die for inclusion in standard package technology
US7217597B2 (en) * 2004-06-22 2007-05-15 Micron Technology, Inc. Die stacking scheme
US8212367B2 (en) 2004-11-10 2012-07-03 Sandisk Il Ltd. Integrated circuit die with logically equivalent bonding pads

Similar Documents

Publication Publication Date Title
JP2009540606A5 (enExample)
JP5320611B2 (ja) スタックダイパッケージ
JP2006093189A5 (enExample)
WO2011142581A3 (ko) 적층형 반도체 패키지
CN102163595A (zh) 堆叠半导体封装
JP2013524552A5 (enExample)
TWI406376B (zh) 晶片封裝構造
CN103236425B (zh) 一种dram双芯片堆叠封装结构和封装工艺
CN101533814B (zh) 芯片级倒装芯片封装构造
CN203721707U (zh) 芯片封装结构
JP2009176978A5 (enExample)
TW201216384A (en) Chip package structure and chip packaging method
CN106409702A (zh) 一种多芯片堆叠封装结构及其制作方法
JP2003318360A5 (enExample)
JP2011003764A5 (ja) 半導体装置
CN1312763C (zh) 芯片埋入式半导体元件封装结构
TWI517354B (zh) 內藏去耦合電容之半導體封裝構造
CN206806338U (zh) 薄型化双芯片的叠接封装结构
US20110304044A1 (en) Stacked chip package structure and its fabrication method
CN102646658A (zh) 半导体封装件及其制造方法
JP2010040955A5 (enExample)
CN203277377U (zh) 一种dram双芯片堆叠封装结构
TW452954B (en) Manufacturing method of multi-chip module
TWI272729B (en) Multi-chip sensor package
TWI534978B (zh) 晶片封裝結構