CN101506975B - 堆叠管芯封装 - Google Patents
堆叠管芯封装 Download PDFInfo
- Publication number
- CN101506975B CN101506975B CN2007800304876A CN200780030487A CN101506975B CN 101506975 B CN101506975 B CN 101506975B CN 2007800304876 A CN2007800304876 A CN 2007800304876A CN 200780030487 A CN200780030487 A CN 200780030487A CN 101506975 B CN101506975 B CN 101506975B
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- circuit die
- wire
- electrical contacts
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US81377806P | 2006-06-15 | 2006-06-15 | |
| US60/813,778 | 2006-06-15 | ||
| US11/801,317 | 2007-05-09 | ||
| US11/801,317 US7535110B2 (en) | 2006-06-15 | 2007-05-09 | Stack die packages |
| PCT/US2007/013821 WO2007146307A2 (en) | 2006-06-15 | 2007-06-13 | Stack die packages |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101506975A CN101506975A (zh) | 2009-08-12 |
| CN101506975B true CN101506975B (zh) | 2011-04-06 |
Family
ID=38666964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007800304876A Active CN101506975B (zh) | 2006-06-15 | 2007-06-13 | 堆叠管芯封装 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US7535110B2 (enExample) |
| EP (1) | EP2033220B1 (enExample) |
| JP (1) | JP5320611B2 (enExample) |
| CN (1) | CN101506975B (enExample) |
| TW (1) | TWI429050B (enExample) |
| WO (1) | WO2007146307A2 (enExample) |
Families Citing this family (51)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5388422B2 (ja) * | 2007-05-11 | 2014-01-15 | スパンション エルエルシー | 半導体装置及びその製造方法 |
| US7677109B2 (en) * | 2008-02-27 | 2010-03-16 | Honeywell International Inc. | Pressure sense die pad layout and method for direct wire bonding to programmable compensation integrated circuit die |
| US8310051B2 (en) | 2008-05-27 | 2012-11-13 | Mediatek Inc. | Package-on-package with fan-out WLCSP |
| US8093722B2 (en) * | 2008-05-27 | 2012-01-10 | Mediatek Inc. | System-in-package with fan-out WLCSP |
| US8896126B2 (en) | 2011-08-23 | 2014-11-25 | Marvell World Trade Ltd. | Packaging DRAM and SOC in an IC package |
| US8253231B2 (en) | 2008-09-23 | 2012-08-28 | Marvell International Ltd. | Stacked integrated circuit package using a window substrate |
| US9009393B1 (en) | 2008-09-23 | 2015-04-14 | Marvell International Ltd. | Hybrid solid-state disk (SSD)/hard disk drive (HDD) architectures |
| US20100213588A1 (en) * | 2009-02-20 | 2010-08-26 | Tung-Hsien Hsieh | Wire bond chip package |
| US8236607B2 (en) * | 2009-06-19 | 2012-08-07 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof |
| US8304917B2 (en) * | 2009-12-03 | 2012-11-06 | Powertech Technology Inc. | Multi-chip stacked package and its mother chip to save interposer |
| TWI501380B (zh) * | 2010-01-29 | 2015-09-21 | Nat Chip Implementation Ct Nat Applied Res Lab | 多基板晶片模組堆疊之三維系統晶片結構 |
| KR101683814B1 (ko) | 2010-07-26 | 2016-12-08 | 삼성전자주식회사 | 관통 전극을 구비하는 반도체 장치 |
| US9490003B2 (en) * | 2011-03-31 | 2016-11-08 | Intel Corporation | Induced thermal gradients |
| US9658678B2 (en) | 2011-03-31 | 2017-05-23 | Intel Corporation | Induced thermal gradients |
| US8674483B2 (en) | 2011-06-27 | 2014-03-18 | Marvell World Trade Ltd. | Methods and arrangements relating to semiconductor packages including multi-memory dies |
| US8823165B2 (en) | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
| US8513817B2 (en) | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
| US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
| KR101894823B1 (ko) | 2011-10-03 | 2018-09-04 | 인벤사스 코포레이션 | 평행한 윈도우를 갖는 다중-다이 와이어 본드 어셈블리를 위한 스터브 최소화 |
| US8513813B2 (en) | 2011-10-03 | 2013-08-20 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
| KR20140085497A (ko) | 2011-10-03 | 2014-07-07 | 인벤사스 코포레이션 | 직교 윈도가 있는 멀티-다이 와이어본드 어셈블리를 위한 스터브 최소화 |
| US8659142B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
| US8917532B2 (en) | 2011-10-03 | 2014-12-23 | Invensas Corporation | Stub minimization with terminal grids offset from center of package |
| US8436457B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
| US8610260B2 (en) | 2011-10-03 | 2013-12-17 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
| US8659139B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
| US8441111B2 (en) | 2011-10-03 | 2013-05-14 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
| CN102446882B (zh) * | 2011-12-30 | 2013-12-04 | 北京工业大学 | 一种半导体封装中封装系统结构及制造方法 |
| US8848392B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support module and microelectronic assembly |
| US8787034B2 (en) | 2012-08-27 | 2014-07-22 | Invensas Corporation | Co-support system and microelectronic assembly |
| US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
| US8848391B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support component and microelectronic assembly |
| US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
| CN103426871B (zh) * | 2013-07-25 | 2017-05-31 | 上海航天测控通信研究所 | 一种高密度混合叠层封装结构及其制作方法 |
| US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
| CN103558903A (zh) * | 2013-11-12 | 2014-02-05 | 上海航天测控通信研究所 | 一种具有抗辐性能的PowerPC计算机模块 |
| US9153560B2 (en) | 2014-01-22 | 2015-10-06 | Qualcomm Incorporated | Package on package (PoP) integrated device comprising a redistribution layer |
| US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
| US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
| JP2016192447A (ja) * | 2015-03-30 | 2016-11-10 | 株式会社東芝 | 半導体装置 |
| BR112017018820A2 (pt) * | 2015-04-14 | 2018-04-24 | Huawei Technologies Co., Ltd. | chip |
| US9871019B2 (en) | 2015-07-17 | 2018-01-16 | Invensas Corporation | Flipped die stack assemblies with leadframe interconnects |
| US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
| US10566310B2 (en) | 2016-04-11 | 2020-02-18 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
| US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
| US9953904B1 (en) | 2016-10-25 | 2018-04-24 | Nxp Usa, Inc. | Electronic component package with heatsink and multiple electronic components |
| CN108336030A (zh) * | 2018-01-16 | 2018-07-27 | 奥肯思(北京)科技有限公司 | 一种多层堆叠系统级封装 |
| KR102699633B1 (ko) | 2019-06-25 | 2024-08-29 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| US11075147B2 (en) * | 2019-07-08 | 2021-07-27 | Texas Instruments Incorporated | Stacked die semiconductor package |
| CN110943077A (zh) * | 2019-11-08 | 2020-03-31 | 关键禾芯科技股份有限公司 | 毫米波应用的多颗晶片封装结构 |
| US20240072002A1 (en) * | 2022-08-23 | 2024-02-29 | Micron Technology, Inc. | Semiconductor devices, assemblies, and associated methods |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6222260B1 (en) * | 1998-05-07 | 2001-04-24 | Vlsi Technology, Inc. | Integrated circuit device with integral decoupling capacitor |
| CN1459857A (zh) * | 2002-05-17 | 2003-12-03 | 三菱电机株式会社 | 半导体器件 |
| CN1474453A (zh) * | 2002-06-27 | 2004-02-11 | �뵼��Ԫ����ҵ�������ι�˾ | 集成电路和分层引线框封装 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0274046A (ja) * | 1988-09-09 | 1990-03-14 | Nec Ic Microcomput Syst Ltd | 半導体集積回路装置 |
| JP3602888B2 (ja) * | 1995-06-14 | 2004-12-15 | 松下電器産業株式会社 | 半導体装置 |
| US5815372A (en) * | 1997-03-25 | 1998-09-29 | Intel Corporation | Packaging multiple dies on a ball grid array substrate |
| US6271598B1 (en) * | 1997-07-29 | 2001-08-07 | Cubic Memory, Inc. | Conductive epoxy flip-chip on chip |
| JP3111312B2 (ja) * | 1997-10-29 | 2000-11-20 | ローム株式会社 | 半導体装置 |
| US6413797B2 (en) | 1997-10-09 | 2002-07-02 | Rohm Co., Ltd. | Semiconductor device and method for making the same |
| JP3494901B2 (ja) * | 1998-09-18 | 2004-02-09 | シャープ株式会社 | 半導体集積回路装置 |
| JP2001196529A (ja) * | 2000-01-17 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置及びその配線方法 |
| JP2001223324A (ja) * | 2000-02-10 | 2001-08-17 | Mitsubishi Electric Corp | 半導体装置 |
| JP2003197856A (ja) * | 2001-12-28 | 2003-07-11 | Oki Electric Ind Co Ltd | 半導体装置 |
| JP2005109068A (ja) * | 2003-09-30 | 2005-04-21 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
| JP4103796B2 (ja) * | 2003-12-25 | 2008-06-18 | 沖電気工業株式会社 | 半導体チップパッケージ及びマルチチップパッケージ |
| JP2005268534A (ja) * | 2004-03-18 | 2005-09-29 | Shinko Electric Ind Co Ltd | 半導体チップおよび積層型半導体装置 |
| US20050212144A1 (en) * | 2004-03-25 | 2005-09-29 | Rugg William L | Stacked die for inclusion in standard package technology |
| US7217597B2 (en) * | 2004-06-22 | 2007-05-15 | Micron Technology, Inc. | Die stacking scheme |
| US8212367B2 (en) | 2004-11-10 | 2012-07-03 | Sandisk Il Ltd. | Integrated circuit die with logically equivalent bonding pads |
-
2007
- 2007-05-09 US US11/801,317 patent/US7535110B2/en active Active
- 2007-06-13 EP EP07809502.3A patent/EP2033220B1/en active Active
- 2007-06-13 WO PCT/US2007/013821 patent/WO2007146307A2/en not_active Ceased
- 2007-06-13 CN CN2007800304876A patent/CN101506975B/zh active Active
- 2007-06-13 JP JP2009515464A patent/JP5320611B2/ja active Active
- 2007-06-15 TW TW096121889A patent/TWI429050B/zh active
-
2009
- 2009-05-01 US US12/434,264 patent/US7825521B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6222260B1 (en) * | 1998-05-07 | 2001-04-24 | Vlsi Technology, Inc. | Integrated circuit device with integral decoupling capacitor |
| CN1459857A (zh) * | 2002-05-17 | 2003-12-03 | 三菱电机株式会社 | 半导体器件 |
| CN1474453A (zh) * | 2002-06-27 | 2004-02-11 | �뵼��Ԫ����ҵ�������ι�˾ | 集成电路和分层引线框封装 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20090212410A1 (en) | 2009-08-27 |
| WO2007146307A2 (en) | 2007-12-21 |
| WO2007146307B1 (en) | 2008-05-22 |
| TW200807670A (en) | 2008-02-01 |
| TWI429050B (zh) | 2014-03-01 |
| EP2033220B1 (en) | 2019-10-16 |
| WO2007146307A3 (en) | 2008-03-06 |
| JP5320611B2 (ja) | 2013-10-23 |
| JP2009540606A (ja) | 2009-11-19 |
| US7535110B2 (en) | 2009-05-19 |
| CN101506975A (zh) | 2009-08-12 |
| US7825521B2 (en) | 2010-11-02 |
| US20080006948A1 (en) | 2008-01-10 |
| EP2033220A2 (en) | 2009-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101506975B (zh) | 堆叠管芯封装 | |
| US7598617B2 (en) | Stack package utilizing through vias and re-distribution lines | |
| CN101330076B (zh) | 穿透硅通道芯片堆叠封装 | |
| CN101355067B (zh) | 多芯片模块的改进的电连接 | |
| US6426559B1 (en) | Miniature 3D multi-chip module | |
| US7888785B2 (en) | Semiconductor package embedded in substrate, system including the same and associated methods | |
| CN101232004A (zh) | 芯片堆叠封装结构 | |
| US10811341B2 (en) | Semiconductor device with through-mold via | |
| US20080237833A1 (en) | Multi-chip semiconductor package structure | |
| CN102057481A (zh) | 具有电源和接地通孔的封装 | |
| US7235870B2 (en) | Microelectronic multi-chip module | |
| CN106449612A (zh) | 存储器芯片堆叠封装结构 | |
| KR20160047841A (ko) | 반도체 패키지 | |
| US20080237831A1 (en) | Multi-chip semiconductor package structure | |
| CN100524736C (zh) | 堆叠型晶片封装结构 | |
| TW202127593A (zh) | 晶片封裝結構 | |
| TWI794021B (zh) | 半導體封裝及其製造方法 | |
| US8344491B2 (en) | Multi-die building block for stacked-die package | |
| US20110304044A1 (en) | Stacked chip package structure and its fabrication method | |
| CN101388380A (zh) | 导线架在芯片及芯片在导线架的多芯片堆叠结构 | |
| CN106298709A (zh) | 低成本扇出式封装结构 | |
| CN206022359U (zh) | 存储器芯片堆叠封装结构 | |
| US20150115437A1 (en) | Universal encapsulation substrate, encapsulation structure and encapsulation method | |
| US20080237832A1 (en) | Multi-chip semiconductor package structure | |
| TWI473242B (zh) | 晶片封裝結構 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200426 Address after: Singapore City Patentee after: Marvell Asia Pte. Ltd. Address before: Ford street, Grand Cayman, Cayman Islands Patentee before: Kaiwei international Co. Effective date of registration: 20200426 Address after: Ford street, Grand Cayman, Cayman Islands Patentee after: Kaiwei international Co. Address before: Hamilton, Bermuda Patentee before: Marvell International Ltd. Effective date of registration: 20200426 Address after: Hamilton, Bermuda Patentee after: Marvell International Ltd. Address before: Babado J San Michael Patentee before: MARVELL WORLD TRADE Ltd. |