JP2009260312A - Ｓｏｉ基板の作製方法及び半導体装置の作製方法 - Google Patents

Ｓｏｉ基板の作製方法及び半導体装置の作製方法 Download PDF

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Publication number
JP2009260312A
JP2009260312A JP2009069449A JP2009069449A JP2009260312A JP 2009260312 A JP2009260312 A JP 2009260312A JP 2009069449 A JP2009069449 A JP 2009069449A JP 2009069449 A JP2009069449 A JP 2009069449A JP 2009260312 A JP2009260312 A JP 2009260312A
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single crystal
crystal semiconductor
semiconductor substrate
substrate
semiconductor layer
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Japanese (ja)
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JP2009260312A5 (https=
Inventor
Shunpei Yamazaki
舜平 山崎
Eriko Nishida
恵里子 西田
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication of JP2009260312A5 publication Critical patent/JP2009260312A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6924—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Electroluminescent Light Sources (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2009069449A 2008-03-26 2009-03-23 Ｓｏｉ基板の作製方法及び半導体装置の作製方法 Withdrawn JP2009260312A (ja)

Priority Applications (1)

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JP2009069449A JP2009260312A (ja) 2008-03-26 2009-03-23 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

Applications Claiming Priority (2)

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JP2008079557 2008-03-26
JP2009069449A JP2009260312A (ja) 2008-03-26 2009-03-23 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

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JP2009260312A5 JP2009260312A5 (https=) 2012-04-12

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JP2014098281A Expired - Fee Related JP5917595B2 (ja) 2008-03-26 2014-05-12 Ｓｏｉ基板の作製方法

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014179641A (ja) * 2008-03-26 2014-09-25 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
WO2016203340A1 (ja) * 2015-06-19 2016-12-22 株式会社半導体エネルギー研究所 表示装置の作製方法、表示装置、電子機器、プロジェクター、及びヘッドマウントディスプレイ

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009260315A (ja) * 2008-03-26 2009-11-05 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法及び半導体装置の作製方法
JP5654206B2 (ja) * 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置
EP2282332B1 (en) * 2009-08-04 2012-06-27 S.O.I. TEC Silicon Method for fabricating a semiconductor substrate
JP5755931B2 (ja) 2010-04-28 2015-07-29 株式会社半導体エネルギー研究所 半導体膜の作製方法、電極の作製方法、２次電池の作製方法、および太陽電池の作製方法
US8962454B2 (en) 2010-11-04 2015-02-24 Tokyo Electron Limited Method of depositing dielectric films using microwave plasma
JP5799740B2 (ja) * 2011-10-17 2015-10-28 信越半導体株式会社 剥離ウェーハの再生加工方法
EP3039711A1 (en) * 2013-08-29 2016-07-06 The Board Of Trustees Of The University Of the Leland Stanford Junior University Method of controlled crack propagation for material cleavage using electromagnetic forces
US10002800B2 (en) * 2016-05-13 2018-06-19 International Business Machines Corporation Prevention of charging damage in full-depletion devices
DE102016112139B3 (de) * 2016-07-01 2018-01-04 Infineon Technologies Ag Verfahren zum Reduzieren einer Verunreinigungskonzentration in einem Halbleiterkörper
SG11201913769RA (en) * 2017-07-14 2020-01-30 Sunedison Semiconductor Ltd Method of manufacture of a semiconductor on insulator structure

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JPH10200080A (ja) * 1996-11-15 1998-07-31 Canon Inc 半導体部材の製造方法
JPH11189493A (ja) * 1997-12-25 1999-07-13 Sumitomo Metal Ind Ltd シリコン単結晶およびエピタキシャルウェーハ
JP2000036583A (ja) * 1998-05-15 2000-02-02 Canon Inc 半導体基板、半導体薄膜の作製方法および多層構造体
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
JP2000109396A (ja) * 1998-08-07 2000-04-18 Nippon Steel Corp シリコン半導体基板及びその製造方法
WO2001027362A1 (en) * 1999-10-15 2001-04-19 Shin-Etsu Handotai Co., Ltd. Silicon single-crystal wafer for epitaxial wafer, epitaxial wafer, methods for producing them, and evaluating method
WO2007142852A2 (en) * 2006-05-31 2007-12-13 Corning Incorporated Producing soi structure using ion shower

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3262621B2 (ja) * 1993-03-11 2002-03-04 松下電器産業株式会社 シリコン酸化膜の形成方法
JP3085184B2 (ja) 1996-03-22 2000-09-04 住友金属工業株式会社 Ｓｏｉ基板及びその製造方法
US6287900B1 (en) * 1996-08-13 2001-09-11 Semiconductor Energy Laboratory Co., Ltd Semiconductor device with catalyst addition and removal
SG65697A1 (en) 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
KR100541882B1 (ko) * 1998-05-01 2006-01-16 왁커 엔에스씨이 코포레이션 실리콘 반도체 기판 및 그의 제조 방법
JP2000012864A (ja) * 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP3395661B2 (ja) * 1998-07-07 2003-04-14 信越半導体株式会社 Ｓｏｉウエーハの製造方法
JP2000082679A (ja) * 1998-07-08 2000-03-21 Canon Inc 半導体基板とその作製方法
JP3921823B2 (ja) 1998-07-15 2007-05-30 信越半導体株式会社 Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP4379943B2 (ja) 1999-04-07 2009-12-09 株式会社デンソー 半導体基板の製造方法および半導体基板製造装置
FR2797714B1 (fr) * 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
JP2002368001A (ja) * 2001-06-07 2002-12-20 Denso Corp 半導体装置及びその製造方法
DE10224160A1 (de) * 2002-05-31 2003-12-18 Advanced Micro Devices Inc Eine Diffusionsbarrierenschicht in Halbleitersubstraten zur Reduzierung der Kupferkontamination von der Rückseite her
WO2003103057A1 (en) * 2002-05-31 2003-12-11 Advanced Micro Devices, Inc. Diffusion barrier layer in semiconductor substrates to reduce copper contamination from the back side
JP4289837B2 (ja) * 2002-07-15 2009-07-01 アプライド マテリアルズ インコーポレイテッド イオン注入方法及びｓｏｉウエハの製造方法
US7129123B2 (en) * 2002-08-27 2006-10-31 Shin-Etsu Handotai Co., Ltd. SOI wafer and a method for producing an SOI wafer
JP2004193515A (ja) * 2002-12-13 2004-07-08 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法
JP2004247610A (ja) * 2003-02-14 2004-09-02 Canon Inc 基板の製造方法
US20040192067A1 (en) * 2003-02-28 2004-09-30 Bruno Ghyselen Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
DE60323098D1 (de) * 2003-09-26 2008-10-02 Soitec Silicon On Insulator Verfahren zur Herstellung vonn Substraten für epitakitisches Wachstum
JP5110772B2 (ja) 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
JP2005340348A (ja) * 2004-05-25 2005-12-08 Sumco Corp Ｓｉｍｏｘ基板の製造方法及び該方法により得られるｓｉｍｏｘ基板
JP4617820B2 (ja) * 2004-10-20 2011-01-26 信越半導体株式会社 半導体ウェーハの製造方法
US7737053B2 (en) * 2004-11-18 2010-06-15 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and manufacturing method of the same
US7579654B2 (en) * 2006-05-31 2009-08-25 Corning Incorporated Semiconductor on insulator structure made using radiation annealing
US7608521B2 (en) * 2006-05-31 2009-10-27 Corning Incorporated Producing SOI structure using high-purity ion shower
JP2008079557A (ja) 2006-09-28 2008-04-10 Shiono Koryo Kk （−）−４β，１０α−アロマデンドランジオールを含有する呈味改善剤
JP2008159811A (ja) * 2006-12-22 2008-07-10 Siltronic Ag Ｓｏｉウェーハの製造方法ならびにｓｏｉウェーハ
US7755113B2 (en) * 2007-03-16 2010-07-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, semiconductor display device, and manufacturing method of semiconductor device
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
KR101440930B1 (ko) * 2007-04-20 2014-09-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판의 제작방법
EP2140480A4 (en) * 2007-04-20 2015-04-22 Semiconductor Energy Lab METHOD FOR PRODUCING AN SOI SUBSTRATE AND SEMICONDUCTOR ARRANGEMENT
KR101436116B1 (ko) * 2007-04-27 2014-09-01 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판 및 그 제조 방법, 및 반도체 장치
EP1993127B1 (en) * 2007-05-18 2013-04-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
US7772054B2 (en) * 2007-06-15 2010-08-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20090117708A1 (en) * 2007-11-01 2009-05-07 Sumco Corporation Method for manufacturing soi substrate
JP2009260315A (ja) * 2008-03-26 2009-11-05 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法及び半導体装置の作製方法
JP5654206B2 (ja) * 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置
EP2105957A3 (en) * 2008-03-26 2011-01-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate and method for manufacturing semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JPH10200080A (ja) * 1996-11-15 1998-07-31 Canon Inc 半導体部材の製造方法
JPH11189493A (ja) * 1997-12-25 1999-07-13 Sumitomo Metal Ind Ltd シリコン単結晶およびエピタキシャルウェーハ
JP2000036583A (ja) * 1998-05-15 2000-02-02 Canon Inc 半導体基板、半導体薄膜の作製方法および多層構造体
JP2000109396A (ja) * 1998-08-07 2000-04-18 Nippon Steel Corp シリコン半導体基板及びその製造方法
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
WO2001027362A1 (en) * 1999-10-15 2001-04-19 Shin-Etsu Handotai Co., Ltd. Silicon single-crystal wafer for epitaxial wafer, epitaxial wafer, methods for producing them, and evaluating method
WO2007142852A2 (en) * 2006-05-31 2007-12-13 Corning Incorporated Producing soi structure using ion shower

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014179641A (ja) * 2008-03-26 2014-09-25 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
WO2016203340A1 (ja) * 2015-06-19 2016-12-22 株式会社半導体エネルギー研究所 表示装置の作製方法、表示装置、電子機器、プロジェクター、及びヘッドマウントディスプレイ
JPWO2016203340A1 (ja) * 2015-06-19 2018-06-28 株式会社半導体エネルギー研究所 表示装置の作製方法、表示装置、電子機器、プロジェクター、及びヘッドマウントディスプレイ
JP2020140213A (ja) * 2015-06-19 2020-09-03 株式会社半導体エネルギー研究所 表示装置

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EP2105957A3 (en) 2011-01-19
EP2105957A2 (en) 2009-09-30
JP5917595B2 (ja) 2016-05-18
JP2014179641A (ja) 2014-09-25
US20090246937A1 (en) 2009-10-01
US8946051B2 (en) 2015-02-03

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