JP2009223971A - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000003491 array Methods 0.000 claims abstract description 14
- 239000011159 matrix material Substances 0.000 claims description 7
- 238000010030 laminating Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 3
- 150000004770 chalcogenides Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910000314 transition metal oxide Inorganic materials 0.000 description 2
- 206010021143 Hypoxia Diseases 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
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Abstract
【解決手段】半導体記憶装置は、半導体基板上に積層された複数のメモリブロック2を備える。メモリブロック2は、複数のビット線BL、複数のビット線BLと交差するように形成された複数のワード線WL、ビット線BLとワード線WLとの各交差部に配置され、一端がビット線BLに他端がワード線WLにそれぞれ接続されたメモリセルMCを含むメモリセルアレイMAが積層されて構成されている。メモリブロック2のビット線BLの一端が接続され、ビット線BLを選択駆動するカラム系制御回路Cと、メモリブロック2のワード線WLの一端が接続され、ワード線WLを選択駆動するロウ系制御回路Rとを備える。カラム系制御回路C及びロウ系制御回路Rはメモリブロック2直下の半導体基板1上に設けられている。
【選択図】図5
Description
Mark Johnson et al.,"512-Mb PROM with a three-dimensional array of diode/antifuse memory cells,"IEEE Journal of Solid-State Circuits, Nov. 2003, Vol.38, No.11, p.1920-1928.
図1は、本発明の第1の実施形態に係る抵抗変化メモリ装置の基本構成、すなわち半導体基板1上のカラム系/ロウ系制御回路が形成される制御回路領域3とその上に積層されたメモリブロック2の構成を示している。
このように構成されたメモリブロック2の下部に設けられるカラム系制御回路及びロウ系制御回路の配置について説明する。
(制御回路の第2の配置例)
次に、第2の実施形態である、メモリブロック2の下部に設けられるカラム系制御回路C及びロウ系制御回路Rの配置の他の例について説明する。
(制御回路の第3の配置例)
次に、第3の実施形態である、メモリブロック2の下部に設けられるカラム系制御回路C及びロウ系制御回路Rの配置のさらに他の例について説明する。
(制御回路の第4の配置例)
次に、第4の実施形態である、メモリブロック2の下部に設けられるカラム系制御回路C及びロウ系制御回路Rの配置のさらに他の例について説明する。
Claims (5)
- 半導体基板と、
この半導体基板上に積層され、互いに平行な複数の第1の配線、前記複数の第1の配線と交差するように形成された互いに平行な複数の第2の配線、及び前記第1の配線と前記第2の配線との各交差部に配置され、一端が前記第1の配線に他端が前記第2の配線にそれぞれ接続されたメモリセルを含むメモリセルアレイと、
前記各メモリセルアレイの直下の前記半導体基板に設けられ前記第1の配線の一端が接続され、前記第1の配線を選択駆動する第1の制御回路と、
前記各メモリセルアレイの直下の前記半導体基板に設けられ前記第2の配線の一端が接続され、前記第2の配線を選択駆動する第2の制御回路と
を備えたことを特徴とする半導体記憶装置。 - 前記各メモリセルアレイは、その直下の前記第1の制御回路及び前記第2の制御回路によってそれぞれ独立に制御されることを特徴とする請求項1記載の半導体記憶装置。
- 前記第1の制御回路及び前記第2の制御回路は、前記各メモリセルアレイの直下の半導体基板にチェッカーボード状に配置されていることを特徴とする請求項1又は2記載の半導体記憶装置。
- 一の前記メモリセルアレイの直下に設けられた前記第1の制御回路及び前記第2の制御回路と、一の前記メモリセルアレイに隣り合う他の前記メモリセルアレイの直下に設けられた前記第1の制御回路及び前記第2の制御回路とは、隣り合う2つの前記メモリセルアレイの境界線を対称軸として線対称に配置されていることを特徴とする請求項1乃至3のいずれか記載の半導体記憶装置。
- 複数の前記メモリセルアレイはマトリクス状に配置されており、
マトリクス状に配列された前記メモリセルアレイのうち同一列の複数のメモリセルアレイ直下の前記第1の制御回路に共通接続された複数の第3の配線と、
マトリクス状に配列された前記メモリセルアレイのうち同一行の複数のメモリセルアレイ直下の前記第2の制御回路に共通接続された複数の第4の配線と、
前記第3の配線の一端が接続され、前記第3の配線を選択駆動する第3の制御回路と、
前記第4の配線の一端が接続され、前記第4の配線を選択駆動する第4の制御回路と
をさらに備えることを特徴とする請求項1乃至4のいずれか記載の半導体記憶装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008068423A JP4709868B2 (ja) | 2008-03-17 | 2008-03-17 | 半導体記憶装置 |
US12/403,781 US8036010B2 (en) | 2008-03-17 | 2009-03-13 | Semiconductor memory device |
US13/226,202 US8149606B2 (en) | 2008-03-17 | 2011-09-06 | Semiconductor memory device |
US13/412,159 US8437162B2 (en) | 2008-03-17 | 2012-03-05 | Semiconductor memory device |
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JP2008068423A JP4709868B2 (ja) | 2008-03-17 | 2008-03-17 | 半導体記憶装置 |
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JP2009223971A true JP2009223971A (ja) | 2009-10-01 |
JP4709868B2 JP4709868B2 (ja) | 2011-06-29 |
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JP2008068423A Expired - Fee Related JP4709868B2 (ja) | 2008-03-17 | 2008-03-17 | 半導体記憶装置 |
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WO2012029638A1 (en) * | 2010-09-03 | 2012-03-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
WO2012060253A1 (en) * | 2010-11-05 | 2012-05-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
KR20120099344A (ko) * | 2011-01-26 | 2012-09-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 기억 장치 및 반도체 장치 |
WO2012121265A1 (en) * | 2011-03-10 | 2012-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and method for manufacturing the same |
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WO2016047254A1 (ja) * | 2014-09-22 | 2016-03-31 | ソニー株式会社 | メモリセルユニットアレイ |
WO2020213240A1 (ja) * | 2019-04-16 | 2020-10-22 | ソニーセミコンダクタソリューションズ株式会社 | 記憶装置および記憶制御装置 |
JP2021122054A (ja) * | 2017-02-16 | 2021-08-26 | マイクロン テクノロジー,インク. | メモリダイ領域の有効利用 |
US11282568B2 (en) | 2019-10-29 | 2022-03-22 | Kioxia Corporation | Semiconductor storage device having a memory unit bonded to a circuit unit and connected to each other by a plurality of bonding metals |
US11705443B2 (en) | 2019-10-16 | 2023-07-18 | Kioxia Corporation | Semiconductor memory device |
US11961556B2 (en) | 2019-11-15 | 2024-04-16 | Micron Technology, Inc. | Socket design for a memory device |
Families Citing this family (19)
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DE602006003994D1 (de) * | 2006-02-03 | 2009-01-15 | Siemens Ag | Verfahren zur Glättung von Wechselstrom aus einer Reihe von Energieerzeugungseinheiten sowie Windkraftanlage mit mehreren Windmühlen mit variabler Rotationsgeschwindigkeit |
JP5039079B2 (ja) * | 2009-03-23 | 2012-10-03 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP2012256821A (ja) | 2010-09-13 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | 記憶装置 |
TWI539453B (zh) * | 2010-09-14 | 2016-06-21 | 半導體能源研究所股份有限公司 | 記憶體裝置和半導體裝置 |
JP2012151453A (ja) | 2010-12-28 | 2012-08-09 | Semiconductor Energy Lab Co Ltd | 半導体装置および半導体装置の駆動方法 |
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US8976577B2 (en) | 2011-04-07 | 2015-03-10 | Tom A. Agan | High density magnetic random access memory |
US9076505B2 (en) | 2011-12-09 | 2015-07-07 | Semiconductor Energy Laboratory Co., Ltd. | Memory device |
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JP6524006B2 (ja) | 2016-03-18 | 2019-06-05 | 東芝メモリ株式会社 | 半導体記憶装置 |
JP2018200738A (ja) * | 2017-05-26 | 2018-12-20 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置 |
JP2019054060A (ja) | 2017-09-13 | 2019-04-04 | 東芝メモリ株式会社 | 半導体記憶装置 |
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2011
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Also Published As
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US20110317463A1 (en) | 2011-12-29 |
US8437162B2 (en) | 2013-05-07 |
US8149606B2 (en) | 2012-04-03 |
US8036010B2 (en) | 2011-10-11 |
US20090230435A1 (en) | 2009-09-17 |
JP4709868B2 (ja) | 2011-06-29 |
US20120163060A1 (en) | 2012-06-28 |
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