JP2009105155A - 半導体装置およびその製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 17
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- 230000015572 biosynthetic process Effects 0.000 claims abstract description 29
- 239000004020 conductor Substances 0.000 claims abstract description 21
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- 229910052710 silicon Inorganic materials 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
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- 108010075750 P-Type Calcium Channels Proteins 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 238000001020 plasma etching Methods 0.000 description 9
- 239000012535 impurity Substances 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
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- 239000000126 substance Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】Si基板1と、フィン11、フィン11の延在方向に平行な面上にゲート絶縁膜13を介して形成される所定の幅のゲート電極14、およびフィン11の延在方向に平行な面上のゲート電極14の両側に形成されるソース/ドレイン領域を含むFinFET10n,10pと、を備え、ゲート電極14上に形成され、応力印加層31,32の形成温度と室温での線膨張係数の差が、フィン11の形成温度と室温での線膨張係数の差と異なる導電性材料によって形成される応力印加層31,32と、応力印加層31,32上に形成され、フィン11よりもヤング率の大きい導電性材料からなるプラグ層33,34と、を備える。
【選択図】 図2−1
Description
図1は、本発明の第1の実施の形態にかかる半導体装置の一例を模式的に示す平面図であり、図2−1は、図1のA−A断面図であり、図2−2(a)は、図1のB−B断面図であり、図2−2(b)は、図1のC−C断面図である。この第1の実施の形態では、1つのSi基板1上にnチャネル型FinFET(以下、nFinFETという)10nとpチャネル型FinFET(以下、pFinFETという)10pが作り込まれたCMOS(Complementary Metal Oxide Semiconductor)デバイスを例に挙げている。また、各FinFET10n,10pは、複数のフィン11のゲート電極、ソース領域およびドレイン領域を共通の配線(プラグ)で接続したマルチFinFET構造を有している。つまり、図1と図2−1において、nFinFET10nで示される部分が1つのFETの役割を有し、pFinFET10pで示される部分が1つのFETの役割を有している。
図5は、本発明の第2の実施の形態にかかる半導体装置の製造方法の手順の一例を模式的に示す断面図である。第1の実施の形態では、応力印加層31,32をそれぞれゲートプラグ30n,30pの一部として構成していたが、図5(e)に示されるように、この第2の実施の形態のFinFETでは、応力印加層61をSi基板1上に形成されるゲート電極14上の全面に積層して形成し、見掛け上ゲート電極が2層構成となるように形成している。つまり、第1の実施の形態のゲートプラグ30n,30pの応力印加層31,32を除去し、Si基板1上に形成されるゲート電極14上の全面に応力印加層61が形成される構造を有する。そして、ゲートプラグ30n,30pは、フィン11の構成材料よりもヤング率の大きな導電性材料からなるプラグ層62のみによって形成される。なお、第1の実施の形態のFinFETと同一の構成要素には同一の符号を付してその説明を省略している。
図6は、本発明の第3の実施の形態にかかる半導体装置の製造方法の手順の一例を模式的に示す断面図である。図6(f)に示されるように、このFinFETは、第2の実施の形態の応力印加層61が多結晶シリコン膜63で形成され、ゲートプラグ30nがSiと合金を形成する金属材料からなるプラグ層64で形成され、ゲート電極14の上部の多結晶シリコン膜63が、プラグ層64を構成する金属と合金化したシリサイド膜65で構成される構造を有している。ここで、ゲートプラグ30nを構成するプラグ層64は、第1および第2の実施の形態と同様に、フィン11の構成材料よりも大きいヤング率を有する導電性材料であるとともに、Siと反応してシリサイドを形成することが可能な金属材料であればよい。また、この第3の実施の形態では、ゲート電極14上部のシリサイド膜65がフィン11に対して圧縮応力を与える圧縮応力印加層として機能している。なお、第1および第2の実施の形態のFinFETと同一の構成要素には同一の符号を付してその説明を省略している。
Claims (5)
- 半導体基板と、
前記半導体基板上に形成され、延在方向にチャネル領域を介してソース/ドレイン領域を有する半導体層からなるフィン、および前記チャネル領域上に絶縁膜を介して形成されるゲート電極を含む電界効果型トランジスタと、
を備える半導体装置において、
前記ゲート電極上に形成され、該応力印加層の形成温度と室温での線膨張係数の差が、前記フィンの前記形成温度と室温での線膨張係数の差と異なる導電性材料によって形成される応力印加層と、
前記応力印加層上に形成され、前記フィンよりもヤング率の大きい導電性材料からなるプラグ層と、
を備えることを特徴とする半導体装置。 - 前記フィンは、n型のチャネルを形成し、
前記応力印加層は、該応力印加層の形成温度と室温での線膨張係数の差が、前記フィンの前記形成温度と室温での線膨張係数の差よりも小さい材料によって構成されることを特徴とする請求項1に記載の半導体装置。 - 前記フィンは、p型のチャネルを形成し、
前記応力印加層は、該応力印加層の形成温度と室温での線膨張係数の差が、前記フィンの前記形成温度と室温での線膨張係数の差よりも大きい材料によって構成されることを特徴とする請求項1に記載の半導体装置。 - 半導体基板と、
前記半導体基板上に形成され、延在方向にチャネル領域を介してソース/ドレイン領域を有する半導体層からなるフィン、および前記チャネル領域上に絶縁膜を介して形成されるゲート電極を含む電界効果型トランジスタと、
を備える半導体装置において、
前記ゲート電極上に、前記フィンの高さ方向に応力を印加するシリサイド膜からなる応力印加層と、
前記応力印加層上に形成される、前記フィンよりもヤング率の大きい導電性材料からなるプラグ層と、
を備えることを特徴とする半導体装置。 - フィンを形成した半導体基板上に、ゲート絶縁膜、ゲート電極およびシリコン膜を順に形成する工程と、
前記ゲート絶縁膜、前記ゲート電極および前記シリコン膜の積層膜を、チャネルを形成する領域に対応する前記フィン上の領域のみを残すようにパターニングする工程と、
前記積層膜をマスクとして、前記積層膜の前記フィンの延在方向に沿った両側の前記フィンに所定の導電型のソース/ドレイン領域を形成する工程と、
前記フィンを形成した前記半導体基板上に層間絶縁膜を形成する工程と、
前記フィンの上部に形成された前記ゲート電極の形成位置にゲートプラグを形成するための開口部を形成する工程と、
前記開口部内にシリコンと合金を形成する金属材料膜を含むプラグ層を形成する工程と、
熱処理を行って前記金属材料膜と接する領域の前記シリコン膜を前記金属材料膜と反応させて、シリサイド膜を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。
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Cited By (3)
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JP2011071517A (ja) * | 2009-09-24 | 2011-04-07 | Taiwan Semiconductor Manufacturing Co Ltd | 金属ゲートとストレッサーを有するゲルマニウムフィンfet |
JP2012038979A (ja) * | 2010-08-09 | 2012-02-23 | Sony Corp | 半導体装置及びその製造方法 |
US8368146B2 (en) | 2010-06-15 | 2013-02-05 | International Business Machines Corporation | FinFET devices |
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JP2007207837A (ja) | 2006-01-31 | 2007-08-16 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
US20120032267A1 (en) * | 2010-08-06 | 2012-02-09 | International Business Machines Corporation | Device and method for uniform sti recess |
US8561003B2 (en) | 2011-07-29 | 2013-10-15 | Synopsys, Inc. | N-channel and P-channel finFET cell architecture with inter-block insulator |
US8595661B2 (en) | 2011-07-29 | 2013-11-26 | Synopsys, Inc. | N-channel and p-channel finFET cell architecture |
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