JP2009081358A - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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Abstract
【解決手段】配線層と絶縁層が積層された配線部材30と、開口部50Xを有した枠状の補強部材50とを有し、配線部材30を開口部50X内に配置すると共に開口部50Xの内壁と配線部材30の外周側壁とを接着部材36を用いて固定する。
【選択図】図2
Description
配線層と絶縁層が積層された配線部材と、
開口部を有した枠状の補強部材とを有し、
前記配線部材を前記開口部内に配置し、前記開口部の内壁と前記配線部材の外周側壁とを接着部材を用いて接着してなる配線基板により解決することができる。
支持体上に配線層と絶縁層を積層して配線部材を形成する工程と、
前記配線部材から前記支持基板を除去する工程と、
開口部が形成された枠状の補強部材の該開口部内に、接着剤を介在させて前記配線部材を配置する工程と、
前記配線部材が配置された前記補強部材を金型に装着し、プレスしつつ加熱することにより前記接着剤を硬化させる工程とを有する配線基板の製造方法により解決することができる。
複数の配線層と絶縁層が積層された配線部材と、
複数の前記絶縁層の内の少なくとも一層に配設されてなる補強部材とを有する配線基板により解決することができる。
支持体上に、配線層と絶縁層を積層した配線部材を形成する工程と、
前記配線部材から前記支持体を除去する工程とを有する配線基板の製造方法であって、
前記配線部材を形成する工程は、
前記複数の絶縁層の内のいずれか一層の絶縁層を形成する際に、先ず補強部材を配設し、次に該補強部材に絶縁樹脂を配設した後に加熱・加圧して前記絶縁樹脂を硬化させ、該補強部材上に絶縁層を形成する工程を含む配線基板の製造方法より解決することができる。
この補強部材53の材料としては、例えば金属(銅或いはアルミニウム等)、ガラス、セラミック、硬質樹脂、及び銅張り積層板(FRグレードがFR−4のもの)等を適用することができる。また補強部材53は、接続パッド18の形成位置に対応して貫通孔53Xが形成されており、よって図9(B)に示すように接続パッド18は貫通孔53Xを介して外部に露出している。このため、図9(A)に示すように、半導体チップ11を第1の外部端子C1となる接続パッド18にフリップチップ接合することができる。
10 支持体
11 半導体チップ
16 レジスト膜
18 接続パッド
18a 第2配線層
18b 第3配線層
18c 第4配線層
19 金型
20 第1絶縁層
22 ソルダーレジスト
29 はんだバンプ
30,32 配線部材
36 接着部材
50,51,52,53 補強部材
50X,51X,52X 開口部
51Y,52Y 鍔部
53X 貫通孔
60 放熱部材
Claims (8)
- 配線層と絶縁層が積層された配線部材と、
開口部を有した枠状の補強部材とを有し、
前記配線部材を前記開口部内に配置し、前記開口部の内壁と前記配線部材の外周側壁とを接着部材を用いて接着してなる配線基板。 - 前記配線部材の表面と前記補強部材の表面とが、少なくともその一面側同士が面一となるよう構成してなる請求項1記載の配線基板。
- 前記配線部材の表面に対し前記補強部材の表面が突出するよう段差部を形成し、該補強部材に前記配線部材を覆う放熱板を配設してなる請求項1記載の配線基板。
- 前記補強部材に内側に向け延出する鍔部を形成し、該鍔部も前記接着部材により前記配線部材に接着してなる請求項1乃至3のいずれか一項に記載の配線基板。
- 支持体上に配線層と絶縁層を積層して配線部材を形成する工程と、
前記配線部材から前記支持基板を除去する工程と、
開口部が形成された枠状の補強部材の該開口部内に、接着剤を介在させて前記配線部材を配置する工程と、
前記配線部材が配置された前記補強部材を金型に装着し、プレスしつつ加熱することにより前記接着剤を硬化させる工程と
を有する配線基板の製造方法。 - 複数の配線層と絶縁層が積層された配線部材と、
複数の前記絶縁層の内の少なくとも一層に配設されてなる補強部材と
を有する配線基板。 - 前記補強部材の表面が粗面とされた請求項6記載の配線基板。
- 支持体上に、配線層と絶縁層を積層した配線部材を形成する工程と、
前記配線部材から前記支持体を除去する工程とを有する配線基板の製造方法であって、
前記配線部材を形成する工程は、
前記複数の絶縁層の内のいずれか一層の絶縁層を形成する際に、先ず補強部材を配設し、次に該補強部材に絶縁樹脂を配設した後に加熱・加圧して前記絶縁樹脂を硬化させ、該補強部材上に絶縁層を形成する工程を含む配線基板の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007250807A JP5025399B2 (ja) | 2007-09-27 | 2007-09-27 | 配線基板及びその製造方法 |
KR1020080090916A KR20090033004A (ko) | 2007-09-27 | 2008-09-17 | 배선 기판 및 그 제조 방법 |
US12/236,118 US20090084585A1 (en) | 2007-09-27 | 2008-09-23 | Wiring substrate and method of manufacturing the same |
TW097137221A TW200921874A (en) | 2007-09-27 | 2008-09-26 | Wiring substrate and method of manufacturing the same |
CN2008101488407A CN101399248B (zh) | 2007-09-27 | 2008-09-27 | 配线基板及其制造的方法 |
CN2011102042880A CN102280435A (zh) | 2007-09-27 | 2008-09-27 | 配线基板及其制造的方法 |
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JP2007250807A JP5025399B2 (ja) | 2007-09-27 | 2007-09-27 | 配線基板及びその製造方法 |
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JP2009081358A true JP2009081358A (ja) | 2009-04-16 |
JP2009081358A5 JP2009081358A5 (ja) | 2010-06-17 |
JP5025399B2 JP5025399B2 (ja) | 2012-09-12 |
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US (1) | US20090084585A1 (ja) |
JP (1) | JP5025399B2 (ja) |
KR (1) | KR20090033004A (ja) |
CN (2) | CN102280435A (ja) |
TW (1) | TW200921874A (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016540390A (ja) * | 2014-09-27 | 2016-12-22 | インテル コーポレイション | 単一方向の加熱を用いる強化ガラスを使用する基板の反り制御 |
JP2018056445A (ja) * | 2016-09-30 | 2018-04-05 | 新光電気工業株式会社 | キャリア基材付き配線基板、キャリア基材付き配線基板の製造方法 |
EP3787026A1 (en) | 2019-09-02 | 2021-03-03 | Canon Kabushiki Kaisha | Mounting substrate to which image sensor is mounted, sensor package and manufacturing method thereof |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI557855B (zh) * | 2011-12-30 | 2016-11-11 | 旭德科技股份有限公司 | 封裝載板及其製作方法 |
CN103379726A (zh) * | 2012-04-17 | 2013-10-30 | 景硕科技股份有限公司 | 线路积层板的复层线路结构 |
KR101369150B1 (ko) * | 2013-10-15 | 2014-03-04 | 주식회사 에스아이 플렉스 | 단차 지그를 이용한 인쇄공법 |
US11081371B2 (en) * | 2016-08-29 | 2021-08-03 | Via Alliance Semiconductor Co., Ltd. | Chip package process |
CN113131291B (zh) * | 2021-03-11 | 2023-05-12 | 东莞市晟合科技有限公司 | 一种搭载电子元器件的连接线及其制作方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197809A (ja) * | 2001-12-26 | 2003-07-11 | Shinko Electric Ind Co Ltd | 半導体装置用パッケージ及びその製造方法並びに半導体装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3635219B2 (ja) * | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | 半導体装置用多層基板及びその製造方法 |
CN101232776B (zh) * | 1999-09-02 | 2011-04-20 | 揖斐电株式会社 | 印刷布线板 |
US7795714B2 (en) * | 2004-08-06 | 2010-09-14 | Supertalent Electronics, Inc. | Two step molding process secured digital card manufacturing method and apparatus |
JP2006179606A (ja) * | 2004-12-21 | 2006-07-06 | Nitto Denko Corp | 配線回路基板 |
JP4526983B2 (ja) * | 2005-03-15 | 2010-08-18 | 新光電気工業株式会社 | 配線基板の製造方法 |
JP3914239B2 (ja) * | 2005-03-15 | 2007-05-16 | 新光電気工業株式会社 | 配線基板および配線基板の製造方法 |
JP4619214B2 (ja) * | 2005-07-04 | 2011-01-26 | 日東電工株式会社 | 配線回路基板 |
CN1925148A (zh) * | 2005-08-29 | 2007-03-07 | 新光电气工业株式会社 | 多层配线基板及其制造方法 |
JP4452222B2 (ja) * | 2005-09-07 | 2010-04-21 | 新光電気工業株式会社 | 多層配線基板及びその製造方法 |
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2007
- 2007-09-27 JP JP2007250807A patent/JP5025399B2/ja not_active Expired - Fee Related
-
2008
- 2008-09-17 KR KR1020080090916A patent/KR20090033004A/ko not_active Application Discontinuation
- 2008-09-23 US US12/236,118 patent/US20090084585A1/en not_active Abandoned
- 2008-09-26 TW TW097137221A patent/TW200921874A/zh unknown
- 2008-09-27 CN CN2011102042880A patent/CN102280435A/zh active Pending
- 2008-09-27 CN CN2008101488407A patent/CN101399248B/zh not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197809A (ja) * | 2001-12-26 | 2003-07-11 | Shinko Electric Ind Co Ltd | 半導体装置用パッケージ及びその製造方法並びに半導体装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2016540390A (ja) * | 2014-09-27 | 2016-12-22 | インテル コーポレイション | 単一方向の加熱を用いる強化ガラスを使用する基板の反り制御 |
US9887110B2 (en) | 2014-09-27 | 2018-02-06 | Intel Corporation | Substrate warpage control using temper glass with uni-directional heating |
JP2018056445A (ja) * | 2016-09-30 | 2018-04-05 | 新光電気工業株式会社 | キャリア基材付き配線基板、キャリア基材付き配線基板の製造方法 |
EP3787026A1 (en) | 2019-09-02 | 2021-03-03 | Canon Kabushiki Kaisha | Mounting substrate to which image sensor is mounted, sensor package and manufacturing method thereof |
US11778293B2 (en) | 2019-09-02 | 2023-10-03 | Canon Kabushiki Kaisha | Mounting substrate to which image sensor is mounted, sensor package and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
CN102280435A (zh) | 2011-12-14 |
TW200921874A (en) | 2009-05-16 |
CN101399248B (zh) | 2011-12-28 |
JP5025399B2 (ja) | 2012-09-12 |
KR20090033004A (ko) | 2009-04-01 |
CN101399248A (zh) | 2009-04-01 |
US20090084585A1 (en) | 2009-04-02 |
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