JP2008535239A5 - - Google Patents

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Publication number
JP2008535239A5
JP2008535239A5 JP2008504019A JP2008504019A JP2008535239A5 JP 2008535239 A5 JP2008535239 A5 JP 2008535239A5 JP 2008504019 A JP2008504019 A JP 2008504019A JP 2008504019 A JP2008504019 A JP 2008504019A JP 2008535239 A5 JP2008535239 A5 JP 2008535239A5
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JP
Japan
Prior art keywords
integrated circuit
monitor structure
filling
monitor
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008504019A
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English (en)
Japanese (ja)
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JP2008535239A (ja
JP5052501B2 (ja
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Priority claimed from US10/907,494 external-priority patent/US7240322B2/en
Application filed filed Critical
Publication of JP2008535239A publication Critical patent/JP2008535239A/ja
Publication of JP2008535239A5 publication Critical patent/JP2008535239A5/ja
Application granted granted Critical
Publication of JP5052501B2 publication Critical patent/JP5052501B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2008504019A 2005-04-04 2005-12-22 製造モニタを集積回路チップに付加する方法 Expired - Fee Related JP5052501B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/907,494 US7240322B2 (en) 2005-04-04 2005-04-04 Method of adding fabrication monitors to integrated circuit chips
US10/907,494 2005-04-04
PCT/US2005/047083 WO2006107356A2 (en) 2005-04-04 2005-12-22 Method of adding fabrication monitors to integrated circuit chips

Publications (3)

Publication Number Publication Date
JP2008535239A JP2008535239A (ja) 2008-08-28
JP2008535239A5 true JP2008535239A5 (enExample) 2008-10-16
JP5052501B2 JP5052501B2 (ja) 2012-10-17

Family

ID=37072118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008504019A Expired - Fee Related JP5052501B2 (ja) 2005-04-04 2005-12-22 製造モニタを集積回路チップに付加する方法

Country Status (6)

Country Link
US (3) US7240322B2 (enExample)
EP (1) EP1869595B1 (enExample)
JP (1) JP5052501B2 (enExample)
CN (1) CN101147148B (enExample)
TW (1) TWI362598B (enExample)
WO (1) WO2006107356A2 (enExample)

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US9773774B1 (en) 2017-03-30 2017-09-26 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
US9768083B1 (en) 2017-06-27 2017-09-19 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
US9786649B1 (en) 2017-06-27 2017-10-10 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
US10096530B1 (en) 2017-06-28 2018-10-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
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