WO2006107356A2 - Method of adding fabrication monitors to integrated circuit chips - Google Patents

Method of adding fabrication monitors to integrated circuit chips Download PDF

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Publication number
WO2006107356A2
WO2006107356A2 PCT/US2005/047083 US2005047083W WO2006107356A2 WO 2006107356 A2 WO2006107356 A2 WO 2006107356A2 US 2005047083 W US2005047083 W US 2005047083W WO 2006107356 A2 WO2006107356 A2 WO 2006107356A2
Authority
WO
WIPO (PCT)
Prior art keywords
shapes
integrated circuit
fill
monitor
monitor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/047083
Other languages
English (en)
French (fr)
Other versions
WO2006107356A3 (en
Inventor
James W. Adkisson
Greg Bazan
John M. Cohn
Matthew S. Grady
Thomas G. Sopchak
David P. Vallett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to EP05855609.3A priority Critical patent/EP1869595B1/en
Priority to JP2008504019A priority patent/JP5052501B2/ja
Priority to CN2005800492611A priority patent/CN101147148B/zh
Publication of WO2006107356A2 publication Critical patent/WO2006107356A2/en
Anticipated expiration legal-status Critical
Publication of WO2006107356A3 publication Critical patent/WO2006107356A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • FIG. 11 is a flowchart of a second embodiment of the present invention.
  • CMP chemical- mechanical-polish
  • damascene or subtractive fill shapes are introduced into the spaces between conductors according to complex fill shape rules, some of which are discussed infra.
  • the present invention will be described using damascene structures (wires, vias, fill shapes and monitor structures as described infra) but it should be understood that the present invention is applicable to subtractive structures (wires, vias, fill shapes and monitor structures) as well. Further, the present invention is applicable to structures wherein the wires are formed by methods other than damascene and subtractive processes but that require a CMP step of a dielectric layer in contact with the wires as part of the structures fabrication process.
  • FIG. 2A is a top view and FIG. 2B is a cross-sectional view through line 2B- 2B of FIG. 2A of a portion of an integrated circuit chip having damascene fill shapes illustrating a first implementation example of the present invention.
  • an electrically probeable opens monitor 160 replaces a subset of damascene fill shapes 150 of FIG. IA and IB.
  • opens monitor 160 comprises damascene fill shaped regions 150A integrally connected in series by damascene wires 165.
  • Filled shaped damascene regions 150A are not damascene fill shapes but have an identical or similar geometry to that of damascene fill shapes.
  • Damascene wires 205 have the width W2.
  • FIG. 6A is a top view and FIG. 6B is a cross-sectional view through line 6B- 6B of FIG. 6A of a portion of an integrated circuit chip having damascene fill shapes illustrating a fifth implementation example of the present invention.
  • an electrically probeable opens and shorts monitor 210 replaces a subset of damascene fill shapes 150 of FIGs. IA and IB.
  • Opens and shorts monitor 210 includes a first damascene serpentine wire 215 and a second damascene serpentine wire 215 spaced a distance S7 apart.
  • a computer program with an appropriate application interface may be created by one of skill in the art and stored on the system or a data and/or program storage device to simplify the practicing of this invention.
  • information for or the computer program created to run the present invention is loaded on the appropriate removable data and/or program storage device 430, fed through data port 460 or typed in using keyboard 445.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
PCT/US2005/047083 2005-04-04 2005-12-22 Method of adding fabrication monitors to integrated circuit chips Ceased WO2006107356A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP05855609.3A EP1869595B1 (en) 2005-04-04 2005-12-22 Method of adding fabrication monitors to integrated circuit chips
JP2008504019A JP5052501B2 (ja) 2005-04-04 2005-12-22 製造モニタを集積回路チップに付加する方法
CN2005800492611A CN101147148B (zh) 2005-04-04 2005-12-22 将制作监视器添加到集成电路芯片的方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/907,494 US7240322B2 (en) 2005-04-04 2005-04-04 Method of adding fabrication monitors to integrated circuit chips
US10/907,494 2005-04-04

Publications (2)

Publication Number Publication Date
WO2006107356A2 true WO2006107356A2 (en) 2006-10-12
WO2006107356A3 WO2006107356A3 (en) 2007-11-22

Family

ID=37072118

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/047083 Ceased WO2006107356A2 (en) 2005-04-04 2005-12-22 Method of adding fabrication monitors to integrated circuit chips

Country Status (6)

Country Link
US (3) US7240322B2 (enExample)
EP (1) EP1869595B1 (enExample)
JP (1) JP5052501B2 (enExample)
CN (1) CN101147148B (enExample)
TW (1) TWI362598B (enExample)
WO (1) WO2006107356A2 (enExample)

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JP2014090187A (ja) * 2013-12-09 2014-05-15 Renesas Electronics Corp 半導体集積回路およびそのパターンレイアウト方法

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US9773774B1 (en) 2017-03-30 2017-09-26 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
US9768083B1 (en) 2017-06-27 2017-09-19 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
US9786649B1 (en) 2017-06-27 2017-10-10 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
US10096530B1 (en) 2017-06-28 2018-10-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
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Cited By (2)

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JP2014090187A (ja) * 2013-12-09 2014-05-15 Renesas Electronics Corp 半導体集積回路およびそのパターンレイアウト方法

Also Published As

Publication number Publication date
US20080017857A1 (en) 2008-01-24
TW200705229A (en) 2007-02-01
EP1869595A2 (en) 2007-12-26
US7240322B2 (en) 2007-07-03
CN101147148A (zh) 2008-03-19
JP2008535239A (ja) 2008-08-28
US20060225023A1 (en) 2006-10-05
US7323278B2 (en) 2008-01-29
CN101147148B (zh) 2010-07-07
US7620931B2 (en) 2009-11-17
JP5052501B2 (ja) 2012-10-17
WO2006107356A3 (en) 2007-11-22
TWI362598B (en) 2012-04-21
EP1869595B1 (en) 2013-08-07
EP1869595A4 (en) 2009-12-16
US20070160920A1 (en) 2007-07-12

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