TWI362598B - Method of adding fabrication monitors to integrated circuit chips - Google Patents

Method of adding fabrication monitors to integrated circuit chips Download PDF

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Publication number
TWI362598B
TWI362598B TW095111771A TW95111771A TWI362598B TW I362598 B TWI362598 B TW I362598B TW 095111771 A TW095111771 A TW 095111771A TW 95111771 A TW95111771 A TW 95111771A TW I362598 B TWI362598 B TW I362598B
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TW
Taiwan
Prior art keywords
shape
integrated circuit
monitoring
area
region
Prior art date
Application number
TW095111771A
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English (en)
Chinese (zh)
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TW200705229A (en
Inventor
James W Adkisson
Greg Bazan
John M Cohn
Matthew S Grady
Thomas G Sopchak
David P Vallett
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Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Ibm filed Critical Ibm
Publication of TW200705229A publication Critical patent/TW200705229A/zh
Application granted granted Critical
Publication of TWI362598B publication Critical patent/TWI362598B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
TW095111771A 2005-04-04 2006-04-03 Method of adding fabrication monitors to integrated circuit chips TWI362598B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/907,494 US7240322B2 (en) 2005-04-04 2005-04-04 Method of adding fabrication monitors to integrated circuit chips

Publications (2)

Publication Number Publication Date
TW200705229A TW200705229A (en) 2007-02-01
TWI362598B true TWI362598B (en) 2012-04-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW095111771A TWI362598B (en) 2005-04-04 2006-04-03 Method of adding fabrication monitors to integrated circuit chips

Country Status (6)

Country Link
US (3) US7240322B2 (enExample)
EP (1) EP1869595B1 (enExample)
JP (1) JP5052501B2 (enExample)
CN (1) CN101147148B (enExample)
TW (1) TWI362598B (enExample)
WO (1) WO2006107356A2 (enExample)

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US9773774B1 (en) 2017-03-30 2017-09-26 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
US9768083B1 (en) 2017-06-27 2017-09-19 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
US9786649B1 (en) 2017-06-27 2017-10-10 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
US10096530B1 (en) 2017-06-28 2018-10-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
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Also Published As

Publication number Publication date
US20080017857A1 (en) 2008-01-24
TW200705229A (en) 2007-02-01
EP1869595A2 (en) 2007-12-26
US7240322B2 (en) 2007-07-03
CN101147148A (zh) 2008-03-19
JP2008535239A (ja) 2008-08-28
US20060225023A1 (en) 2006-10-05
US7323278B2 (en) 2008-01-29
CN101147148B (zh) 2010-07-07
WO2006107356A2 (en) 2006-10-12
US7620931B2 (en) 2009-11-17
JP5052501B2 (ja) 2012-10-17
WO2006107356A3 (en) 2007-11-22
EP1869595B1 (en) 2013-08-07
EP1869595A4 (en) 2009-12-16
US20070160920A1 (en) 2007-07-12

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