JP5052501B2 - 製造モニタを集積回路チップに付加する方法 - Google Patents
製造モニタを集積回路チップに付加する方法 Download PDFInfo
- Publication number
- JP5052501B2 JP5052501B2 JP2008504019A JP2008504019A JP5052501B2 JP 5052501 B2 JP5052501 B2 JP 5052501B2 JP 2008504019 A JP2008504019 A JP 2008504019A JP 2008504019 A JP2008504019 A JP 2008504019A JP 5052501 B2 JP5052501 B2 JP 5052501B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- monitor
- damascene
- filling
- mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
電圧コントラスト測定は、引用により全体が本明細書に組み入れられる、Mahant−Shetti他による特許文献1において詳細に説明されている。
105:第1誘電体層
115:第2誘電体層
120:第1誘電体層の上面
125A、125B、125C:ダマシン配線
130A、130B、130C:ダマシン配線125A、125B、125Cの上面
135:第2誘電体層の上面
140、250:ダマシン・ビア
145、165、180A、180B、205、235、240:ダマシン配線
150:ダマシン充填型
155:ダマシン充填型の上面
W1:ダマシン充填型の幅
W2:ダマシン配線の幅
L1:ダマシン充填型の長さ
S1:隣接するダマシン充填型の間の間隔
S2:ダマシン充填型とダマシン配線の間の最小間隔
S3:ダマシン充填型とダマシン配線の間の最大間隔
S4、S5:スペースの幅
S6:ダマシン中央パッド190とダマシン外側パッド150Eの間の距離
S7:第1ダマシン蛇行配線215と第2ダマシン蛇行配線220の間の距離
160:開路モニタ
150A、150B:ダマシン充填型領域
150C、150D:ダマシン充填型領域150Bの半領域
170:短絡モニタ
175A、175B:間隔
185,245:電圧コントラスト短絡モニタ
190,200:ダマシン中央パッド
150E:ダマシン外側パッド
195:電圧コントラスト開路モニタ
210:開路及び短絡モニタ
215、220:ダマシン蛇行配線
225:ビア・チェーン・モニタ
255:ダマシン・パッド
260:ダマシン・スタッド
265:拡散コンタクト
270A:NFET
270B:PFET
275A、275B:チャネル
280A、280B:ソース/ドレイン
285:ウェル
290A、290B:ゲート電極
295:誘電体分離
400:コンピュータ・システム
405:中央処理装置(CPU)
410:システム・バス
415:ランダム・アクセス・メモリ(RAM)
420:読み出し専用メモリ(ROM)
425:入力/出力(I/O)アダプタ
430:リムーバブル・データ及び又はプログラム記憶装置
435:大容量データ及び又はプログラム記憶装置
440:ユーザ・インタフェース・アダプタ
445:キーボード
450:マウス
455:ポート・アダプタ
460:ポート・データ
465:ディスプレイ・アダプタ
470:ディスプレイ装置
Claims (10)
- 集積回路を設計する方法であって、
(a)前記集積回路の集積回路設計の、多数の集積回路素子型を含むフォトマスク・レベル設計を作成するステップと、
(b)隣接する集積回路素子型の間に前記フォトマスク・レベル設計の領域を指定するステップであって、前記指定された領域は、充填型ルールに基づいて前記隣接する集積回路素子の間に充填型を配置するのに必要な程度に十分に大きく、前記充填型は前記集積回路の動作には必要とされない、前記指定するステップと、
(c)前記多数の集積回路素子型に接続されない充填型を、前記指定された領域内に配置するステップと、
(d)前記指定された領域の少なくとも1つから、選択された数の前記充填型を除去して、1つ又は複数のモニタ型領域を前記指定された領域の前記少なくとも1つの内部に設けるステップと、
(e)前記集積回路の動作には必要とされないモニタ構造体のモニタ構造体型の1つ又は複数を、前記モニタ型領域内に配置するステップと
を含み、前記各ステップは、(a)、(b)、(c)、(d)、(e)の順に実行される、前記方法。 - 前記ステップ(d)の前に、(f)あらゆる指定された領域が前記1つ又は複数のモニタ構造体型を収容するのに十分な大きさを有するかどうかを判定するステップ
をさらに含む、請求項1に記載の方法。 - 集積回路を設計する方法であって、
(a)前記集積回路の集積回路設計の、多数の集積回路素子型を含むフォトマスク・レベル設計を作成するステップと、
(c)前記集積回路の動作には必要とされないモニタ構造体のモニタ構造体型の1つ又は複数を、隣接する集積回路素子型の間に配置するための領域を指定し、前記モニタ構造体型の1つ又は複数を該指定された領域内に配置するステップと、
(b)前記隣接する集積回路素子型の間に前記フォトマスク・レベル設計の領域を指定するステップであって、前記指定された領域は、充填型ルールに基づいて前記隣接する集積回路素子の間に充填型を配置するのに必要な程度に十分に大きく、前記充填型は前記集積回路の動作には必要とされない、前記指定するステップと、
(d)前記多数の集積回路素子型に接続されない充填型を、前記ステップ(b)において指定された領域内に配置するステップと
を含み、前記各ステップは(a)、(c)、(b)そして(d)の順に実行される、前記方法。 - 前記1つ又は複数のモニタ構造体型の1つの一部分は、それがなければ前記1つ又は複数のモニタ構造体型の少なくとも1つの前記一部分と同じ場所を占有することになる前記充填型の1つの形状と同じ形状を有する、請求項1〜3のいずれか1項に記載の方法。
- 前記1つ又は複数のモニタ構造体型を含む選択された領域は、前記モニタ構造体型の代わりに前記充填型が該充填型ルールに基づいて前記選択された領域内に配置されたとしたときの空きスペースに対する充填型の比に等しい、空きスペースに対するモニタ構造体型の比を有する、請求項1〜4のいずれか1項に記載の方法。
- 前記モニタ構造体は、前記集積回路の製造中のプロセスによって誘起される欠陥、前記集積回路の製造中又はその後の前記集積回路又は前記集積回路素子の電気特性、或いは、前記集積回路の製造中又はその後の前記集積回路又は前記集積回路素子の性能基準を監視するための、モニタ又は該モニタの一部分である、請求項1〜5のいずれか1項に記載の方法。
- 前記プロセスによって誘起される欠陥は、開路欠陥及び短絡欠陥のいずれか又は両者を含み、前記電気特性は、抵抗、キャパシタンス及びインダクタンスのいずれかを含み、前記性能基準は、信号伝播周波数及びトランジスタの切り替え速度のいずれかを含む、請求項6に記載の方法。
- (g)前記フォトマスク・レベル設計からマスク・データセットを作成するステップと、
(h)前記集積回路の物理レベルを製造するために、前記マスク・データセットを用いてウェハ上にパターンを形成するステップと
をさらに含む、請求項1〜7のいずれか1項に記載の設計方法を用いた集積回路を製造する方法。 - 前記ステップ(h)の後に、前記集積回路の前記物理レベルの製造中に化学機械研磨プロセスを実行するステップ
をさらに含む、請求項8に記載の方法。 - 集積回路を設計又は製造するためのコンピュータ・プログラムであって、コンピュータに、請求項1〜9のいずれか1項に記載の方法の各ステップを実行させる前記コンピュータ・プログラム。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/907,494 | 2005-04-04 | ||
US10/907,494 US7240322B2 (en) | 2005-04-04 | 2005-04-04 | Method of adding fabrication monitors to integrated circuit chips |
PCT/US2005/047083 WO2006107356A2 (en) | 2005-04-04 | 2005-12-22 | Method of adding fabrication monitors to integrated circuit chips |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008535239A JP2008535239A (ja) | 2008-08-28 |
JP2008535239A5 JP2008535239A5 (ja) | 2008-10-16 |
JP5052501B2 true JP5052501B2 (ja) | 2012-10-17 |
Family
ID=37072118
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008504019A Expired - Fee Related JP5052501B2 (ja) | 2005-04-04 | 2005-12-22 | 製造モニタを集積回路チップに付加する方法 |
Country Status (6)
Country | Link |
---|---|
US (3) | US7240322B2 (ja) |
EP (1) | EP1869595B1 (ja) |
JP (1) | JP5052501B2 (ja) |
CN (1) | CN101147148B (ja) |
TW (1) | TWI362598B (ja) |
WO (1) | WO2006107356A2 (ja) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7240322B2 (en) * | 2005-04-04 | 2007-07-03 | International Business Machines Corporation | Method of adding fabrication monitors to integrated circuit chips |
US7926006B2 (en) * | 2007-02-23 | 2011-04-12 | International Business Machines Corporation | Variable fill and cheese for mitigation of BEOL topography |
JP5431661B2 (ja) * | 2007-09-05 | 2014-03-05 | ルネサスエレクトロニクス株式会社 | 半導体集積回路およびそのパターンレイアウト方法 |
US7999566B2 (en) * | 2007-12-31 | 2011-08-16 | Hitachi Global Storage Technologies, Netherlands B.V. | Wafer level testing |
US8716135B1 (en) | 2008-01-30 | 2014-05-06 | Cadence Design Systems, Inc. | Method of eliminating a lithography operation |
JPWO2009119642A1 (ja) * | 2008-03-26 | 2011-07-28 | 日本電気株式会社 | サービス応答性能分析装置、方法、及びプログラム並びにそれを記録した記録媒体 |
US20110101534A1 (en) * | 2009-11-04 | 2011-05-05 | International Business Machines Corporation | Automated short length wire shape strapping and methods of fabricting the same |
US8470674B2 (en) * | 2011-01-03 | 2013-06-25 | International Business Machines Corporation | Structure, method and system for complementary strain fill for integrated circuit chips |
TWI447887B (zh) * | 2011-06-01 | 2014-08-01 | 矽品精密工業股份有限公司 | 電路元件孔鏈結構及其佈局方法 |
US9524916B2 (en) * | 2012-10-31 | 2016-12-20 | International Business Machines Corporation | Structures and methods for determining TDDB reliability at reduced spacings using the structures |
US9059052B2 (en) | 2013-05-16 | 2015-06-16 | International Business Machines Corporation | Alternating open-ended via chains for testing via formation and dielectric integrity |
US9672316B2 (en) | 2013-07-17 | 2017-06-06 | Arm Limited | Integrated circuit manufacture using direct write lithography |
JP5647328B2 (ja) * | 2013-12-09 | 2014-12-24 | ルネサスエレクトロニクス株式会社 | 半導体集積回路およびそのパターンレイアウト方法 |
US9519210B2 (en) * | 2014-11-21 | 2016-12-13 | International Business Machines Corporation | Voltage contrast characterization structures and methods for within chip process variation characterization |
US9799575B2 (en) * | 2015-12-16 | 2017-10-24 | Pdf Solutions, Inc. | Integrated circuit containing DOEs of NCEM-enabled fill cells |
US10199283B1 (en) | 2015-02-03 | 2019-02-05 | Pdf Solutions, Inc. | Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage |
US10978438B1 (en) | 2015-12-16 | 2021-04-13 | Pdf Solutions, Inc. | IC with test structures and E-beam pads embedded within a contiguous standard cell area |
US10593604B1 (en) | 2015-12-16 | 2020-03-17 | Pdf Solutions, Inc. | Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells |
US9929063B1 (en) | 2016-04-04 | 2018-03-27 | Pdf Solutions, Inc. | Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates |
US9653446B1 (en) | 2016-04-04 | 2017-05-16 | Pdf Solutions, Inc. | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells |
US9905553B1 (en) | 2016-04-04 | 2018-02-27 | Pdf Solutions, Inc. | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells |
US9748153B1 (en) | 2017-03-29 | 2017-08-29 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure |
US9773774B1 (en) | 2017-03-30 | 2017-09-26 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells |
US9768083B1 (en) | 2017-06-27 | 2017-09-19 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells |
US9786649B1 (en) | 2017-06-27 | 2017-10-10 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells |
US9865583B1 (en) | 2017-06-28 | 2018-01-09 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells |
US10096530B1 (en) | 2017-06-28 | 2018-10-09 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS602775B2 (ja) * | 1981-08-28 | 1985-01-23 | 富士通株式会社 | モニタ機能付大規模集積回路及びその製造方法 |
US4801869A (en) * | 1987-04-27 | 1989-01-31 | International Business Machines Corporation | Semiconductor defect monitor for diagnosing processing-induced defects |
US5159752A (en) | 1989-03-22 | 1992-11-03 | Texas Instruments Incorporated | Scanning electron microscope based parametric testing method and apparatus |
JPH0645439A (ja) * | 1992-07-23 | 1994-02-18 | Nec Corp | 半導体装置 |
US5736863A (en) | 1996-06-19 | 1998-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Abatement of electron beam charging distortion during dimensional measurements of integrated circuit patterns with scanning electron microscopy by the utilization of specially designed test structures |
US5723874A (en) * | 1996-06-24 | 1998-03-03 | International Business Machines Corporation | Dishing and erosion monitor structure for damascene metal processing |
US5781445A (en) | 1996-08-22 | 1998-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Plasma damage monitor |
US5959459A (en) * | 1996-12-10 | 1999-09-28 | International Business Machines Corporation | Defect monitor and method for automated contactless inline wafer inspection |
US6147361A (en) | 1997-02-07 | 2000-11-14 | Taiwan Semiconductor Manufacturing Company | Polysilicon electromigration sensor which can detect and monitor electromigration in composite metal lines on integrated circuit structures with improved sensitivity |
US5900644A (en) | 1997-07-14 | 1999-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test site and a method of monitoring via etch depths for semiconductor devices |
US5952674A (en) * | 1998-03-18 | 1999-09-14 | International Business Machines Corporation | Topography monitor |
US6121156A (en) * | 1998-04-28 | 2000-09-19 | Cypress Semiconductor Corporation | Contact monitor, method of forming same and method of analyzing contact-, via-and/or trench-forming processes in an integrated circuit |
US6030732A (en) | 1999-01-07 | 2000-02-29 | Taiwan Semiconductor Manufacturing Company | In-situ etch process control monitor |
JP2000294730A (ja) * | 1999-04-09 | 2000-10-20 | Mitsubishi Electric Corp | システムlsiチップ及びその製造方法 |
JP2001077114A (ja) * | 1999-09-03 | 2001-03-23 | Seiko Epson Corp | ダミーパターンの設計方法、ダミーパターンの設計装置、ダミーパターンを有する半導体装置及びその製造方法 |
US6834117B1 (en) * | 1999-11-30 | 2004-12-21 | Texas Instruments Incorporated | X-ray defect detection in integrated circuit metallization |
JP4307664B2 (ja) * | 1999-12-03 | 2009-08-05 | 株式会社ルネサステクノロジ | 半導体装置 |
US6433561B1 (en) * | 1999-12-14 | 2002-08-13 | Kla-Tencor Corporation | Methods and apparatus for optimizing semiconductor inspection tools |
US6509197B1 (en) * | 1999-12-14 | 2003-01-21 | Kla-Tencor Corporation | Inspectable buried test structures and methods for inspecting the same |
US6771806B1 (en) * | 1999-12-14 | 2004-08-03 | Kla-Tencor | Multi-pixel methods and apparatus for analysis of defect information from test structures on semiconductor devices |
US6362634B1 (en) * | 2000-01-14 | 2002-03-26 | Advanced Micro Devices, Inc. | Integrated defect monitor structures for conductive features on a semiconductor topography and method of use |
US6576923B2 (en) * | 2000-04-18 | 2003-06-10 | Kla-Tencor Corporation | Inspectable buried test structures and methods for inspecting the same |
US6787271B2 (en) * | 2000-07-05 | 2004-09-07 | Numerical Technologies, Inc. | Design and layout of phase shifting photolithographic masks |
US6808944B1 (en) * | 2000-07-24 | 2004-10-26 | Cypress Semiconductor Corporation | Structure and method for monitoring a semiconductor process, and method of making such a structure |
KR100363093B1 (ko) * | 2000-07-28 | 2002-12-05 | 삼성전자 주식회사 | 반도체 소자의 층간 절연막 평탄화 방법 |
JP2002110809A (ja) * | 2000-10-02 | 2002-04-12 | Mitsubishi Electric Corp | ダミーパターンの設計方法およびそれを用いた半導体装置の製造方法 |
US6504225B1 (en) * | 2001-04-18 | 2003-01-07 | Advanced Micro Devices, Inc. | Teos seaming scribe line monitor |
JP3556647B2 (ja) * | 2001-08-21 | 2004-08-18 | 沖電気工業株式会社 | 半導体素子の製造方法 |
EP1430316A1 (en) * | 2001-09-28 | 2004-06-23 | PDF Solutions, Inc. | Test structures for estimating dishing and erosion effects in copper damascene technology |
US6624031B2 (en) * | 2001-11-20 | 2003-09-23 | International Business Machines Corporation | Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure |
TWI221014B (en) * | 2002-02-28 | 2004-09-11 | Pdf Solutions Inc | Back end of line clone test vehicle |
KR100476890B1 (ko) * | 2002-04-11 | 2005-03-17 | 삼성전자주식회사 | 검사패턴 및 이를 이용한 화학적기계적 연마공정 제어방법 |
KR100428791B1 (ko) * | 2002-04-17 | 2004-04-28 | 삼성전자주식회사 | 저유전율 절연막을 이용한 듀얼 다마신 배선 형성방법 |
US6823496B2 (en) * | 2002-04-23 | 2004-11-23 | International Business Machines Corporation | Physical design characterization system |
US6623995B1 (en) * | 2002-10-30 | 2003-09-23 | Taiwan Semiconductor Manufacturing Company | Optimized monitor method for a metal patterning process |
US6774395B1 (en) * | 2003-01-15 | 2004-08-10 | Advanced Micro Devices, Inc. | Apparatus and methods for characterizing floating body effects in SOI devices |
US7507598B2 (en) * | 2003-06-06 | 2009-03-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Image sensor fabrication method and structure |
US7089522B2 (en) * | 2003-06-11 | 2006-08-08 | Chartered Semiconductor Manufacturing, Ltd. | Device, design and method for a slot in a conductive area |
US7135344B2 (en) * | 2003-07-11 | 2006-11-14 | Applied Materials, Israel, Ltd. | Design-based monitoring |
US6936920B2 (en) * | 2003-08-29 | 2005-08-30 | Lsi Logic Corporation | Voltage contrast monitor for integrated circuit defects |
US6998866B1 (en) * | 2004-07-27 | 2006-02-14 | International Business Machines Corporation | Circuit and method for monitoring defects |
US7194706B2 (en) * | 2004-07-27 | 2007-03-20 | International Business Machines Corporation | Designing scan chains with specific parameter sensitivities to identify process defects |
US7093213B2 (en) * | 2004-08-13 | 2006-08-15 | International Business Machines Corporation | Method for designing an integrated circuit defect monitor |
US7240322B2 (en) * | 2005-04-04 | 2007-07-03 | International Business Machines Corporation | Method of adding fabrication monitors to integrated circuit chips |
-
2005
- 2005-04-04 US US10/907,494 patent/US7240322B2/en active Active
- 2005-12-22 EP EP05855609.3A patent/EP1869595B1/en active Active
- 2005-12-22 CN CN2005800492611A patent/CN101147148B/zh not_active Expired - Fee Related
- 2005-12-22 WO PCT/US2005/047083 patent/WO2006107356A2/en active Application Filing
- 2005-12-22 JP JP2008504019A patent/JP5052501B2/ja not_active Expired - Fee Related
-
2006
- 2006-04-03 TW TW095111771A patent/TWI362598B/zh not_active IP Right Cessation
-
2007
- 2007-03-19 US US11/687,731 patent/US7323278B2/en active Active
- 2007-09-24 US US11/859,890 patent/US7620931B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20060225023A1 (en) | 2006-10-05 |
US20080017857A1 (en) | 2008-01-24 |
EP1869595B1 (en) | 2013-08-07 |
TW200705229A (en) | 2007-02-01 |
WO2006107356A3 (en) | 2007-11-22 |
US20070160920A1 (en) | 2007-07-12 |
US7620931B2 (en) | 2009-11-17 |
JP2008535239A (ja) | 2008-08-28 |
TWI362598B (en) | 2012-04-21 |
EP1869595A4 (en) | 2009-12-16 |
EP1869595A2 (en) | 2007-12-26 |
CN101147148A (zh) | 2008-03-19 |
US7240322B2 (en) | 2007-07-03 |
US7323278B2 (en) | 2008-01-29 |
WO2006107356A2 (en) | 2006-10-12 |
CN101147148B (zh) | 2010-07-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5052501B2 (ja) | 製造モニタを集積回路チップに付加する方法 | |
TWI594142B (zh) | 使測試單元及虛擬單元包含於積體電路之佈局中的方法 | |
US8245180B2 (en) | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same | |
US9892224B2 (en) | Method of forming masks | |
US8225239B2 (en) | Methods for defining and utilizing sub-resolution features in linear topology | |
US7859111B2 (en) | Computer implemented method for designing a semiconductor device, an automated design system and a semiconductor device | |
US8129095B2 (en) | Methods, photomasks and methods of fabricating photomasks for improving damascene wire uniformity without reducing performance | |
KR20150088805A (ko) | 더블 패턴 리소그래피를 위한 금속 밀도 분포 | |
US9607852B2 (en) | Methods of dividing layouts and methods of manufacturing semiconductor devices using the same | |
US7089522B2 (en) | Device, design and method for a slot in a conductive area | |
JP2005208473A (ja) | 自動設計装置,自動設計方法,及びこれらを用いて製造可能なレチクルセット,半導体集積回路 | |
US20140208285A1 (en) | Self-aligned double patterning via enclosure design | |
TWI443541B (zh) | 多重圖形化用之佈局定義、元件庫產生、及積體電路設計之方法和光罩組 | |
TW202243171A (zh) | 半導體元件 | |
US7315054B1 (en) | Decoupling capacitor density while maintaining control over ACLV regions on a semiconductor integrated circuit | |
JP2005303089A (ja) | 半導体装置 | |
US11387144B2 (en) | Semiconductor device and method of manufacturing the same | |
CN114091291B (zh) | 一种半导体版图的监控方法及系统 | |
US20220327277A1 (en) | Routing structure of semiconductor device and forming method thereof | |
TW202403586A (zh) | 包括鄰接塊的積體電路和設計積體電路的佈局的方法 | |
TW201618167A (zh) | 半導體元件的製作以及檢測方法 | |
US20140075395A1 (en) | Semiconductor integrated circuit design apparatus, semiconductor integrated circuit design method, and storage medium | |
Levinson et al. | Kye et al.(43) Pub. Date: Jul. 24, 2014 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080822 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080822 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111122 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20111124 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20111220 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111220 |
|
RD12 | Notification of acceptance of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7432 Effective date: 20111220 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20111222 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120214 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20120420 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120420 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120524 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120525 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20120525 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120702 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20120702 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20120702 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120724 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150803 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |