CN101147148B - 将制作监视器添加到集成电路芯片的方法 - Google Patents

将制作监视器添加到集成电路芯片的方法 Download PDF

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Publication number
CN101147148B
CN101147148B CN2005800492611A CN200580049261A CN101147148B CN 101147148 B CN101147148 B CN 101147148B CN 2005800492611 A CN2005800492611 A CN 2005800492611A CN 200580049261 A CN200580049261 A CN 200580049261A CN 101147148 B CN101147148 B CN 101147148B
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integrated circuit
shapes
monitor
fill
shape
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Expired - Fee Related
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Chinese (zh)
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CN101147148A (zh
Inventor
J·W·阿基森
G·巴赞
J·M·科恩
M·S·格雷迪
T·G·索普查克
D·P·瓦尔特
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CN2005800492611A 2005-04-04 2005-12-22 将制作监视器添加到集成电路芯片的方法 Expired - Fee Related CN101147148B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/907,494 US7240322B2 (en) 2005-04-04 2005-04-04 Method of adding fabrication monitors to integrated circuit chips
US10/907,494 2005-04-04
PCT/US2005/047083 WO2006107356A2 (en) 2005-04-04 2005-12-22 Method of adding fabrication monitors to integrated circuit chips

Publications (2)

Publication Number Publication Date
CN101147148A CN101147148A (zh) 2008-03-19
CN101147148B true CN101147148B (zh) 2010-07-07

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CN2005800492611A Expired - Fee Related CN101147148B (zh) 2005-04-04 2005-12-22 将制作监视器添加到集成电路芯片的方法

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US (3) US7240322B2 (enExample)
EP (1) EP1869595B1 (enExample)
JP (1) JP5052501B2 (enExample)
CN (1) CN101147148B (enExample)
TW (1) TWI362598B (enExample)
WO (1) WO2006107356A2 (enExample)

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US9627370B1 (en) 2016-04-04 2017-04-18 Pdf Solutions, Inc. Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells
US9748153B1 (en) 2017-03-29 2017-08-29 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure
US9773774B1 (en) 2017-03-30 2017-09-26 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
US9768083B1 (en) 2017-06-27 2017-09-19 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
US9786649B1 (en) 2017-06-27 2017-10-10 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
US10096530B1 (en) 2017-06-28 2018-10-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
US9865583B1 (en) 2017-06-28 2018-01-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells

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Also Published As

Publication number Publication date
US20080017857A1 (en) 2008-01-24
TW200705229A (en) 2007-02-01
EP1869595A2 (en) 2007-12-26
US7240322B2 (en) 2007-07-03
CN101147148A (zh) 2008-03-19
JP2008535239A (ja) 2008-08-28
US20060225023A1 (en) 2006-10-05
US7323278B2 (en) 2008-01-29
WO2006107356A2 (en) 2006-10-12
US7620931B2 (en) 2009-11-17
JP5052501B2 (ja) 2012-10-17
WO2006107356A3 (en) 2007-11-22
TWI362598B (en) 2012-04-21
EP1869595B1 (en) 2013-08-07
EP1869595A4 (en) 2009-12-16
US20070160920A1 (en) 2007-07-12

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