JP2008513925A - 集積回路を誤った動作から保護する方法および装置 - Google Patents
集積回路を誤った動作から保護する方法および装置 Download PDFInfo
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- JP2008513925A JP2008513925A JP2007532356A JP2007532356A JP2008513925A JP 2008513925 A JP2008513925 A JP 2008513925A JP 2007532356 A JP2007532356 A JP 2007532356A JP 2007532356 A JP2007532356 A JP 2007532356A JP 2008513925 A JP2008513925 A JP 2008513925A
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- 238000000034 method Methods 0.000 title claims description 10
- 238000012545 processing Methods 0.000 claims abstract description 35
- 230000015654 memory Effects 0.000 claims abstract description 32
- 238000001514 detection method Methods 0.000 claims abstract description 27
- 230000004044 response Effects 0.000 claims abstract description 19
- 238000007599 discharging Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000008672 reprogramming Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Security & Cryptography (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Power Sources (AREA)
Abstract
)
Description
図の要素は、簡潔にするため、また、明確にするために示され、必ずしも、一定比例尺に従って描かれていないことを当業者は理解する。たとえば、図の要素の一部の寸法は、本発明の実施形態の理解をよくするのを助けるために、他の要素に対して誇張されてもよい。
Claims (10)
- 命令を実行する処理ユニットと、
同処理ユニットに結合し、同処理ユニットから制御信号を受信することに応答して第1の所定の動作を実施する回路と、
集積回路に供給される電源電圧が、所定の電圧レベルより低いかどうかを判定する低電圧検出回路と、を備える集積回路であって、
前記第1の所定の動作が前記回路で行われることに応答して、前記低電圧検出回路の動作をイネーブルする電圧検出イネーブル信号が供給され、前記電源電圧が所定の電圧レベルより低い場合、前記低電圧検出回路によって、集積回路で第2の所定の動作が始動されるようにする集積回路。 - 前記回路は不揮発性メモリであり、前記第1の所定の動作は、前記不揮発性メモリのプログラム動作または消去動作のうちの一方であり、前記第2の所定の動作は、前記第1の所定の動作を停止させる請求項1に記載の集積回路。
- 前記不揮発性メモリに結合するチャージポンプをさらに備え、前記第2の所定の動作は、前記チャージポンプをディスエーブルにする請求項2に記載の集積回路。
- 前記低電圧検出回路は、
プログラム信号および消去信号に応答して第1検出イネーブル信号を供給する第1論理回路と、
電源端子に結合し、前記電源端子の電圧が所定レベルを超える場合、前記検出イネーブル信号に応答して電圧有効信号をアサートする電圧検出回路と、
前記電圧有効信号に応答してチャージポンプイネーブル信号を生成する第2論理回路と、
前記チャージポンプイネーブル信号がアサートされていないことに応答して放電するチャージポンプと、を備える請求項1に記載の集積回路。 - 前記電圧検出回路は、低電圧禁止回路の一部分である請求項4に記載の集積回路。
- 前記低電圧禁止回路は、
第2検出イネーブル信号を供給する出力を有する制御レジスタビットと、
前記第1検出イネーブル信号および前記第2検出イネーブル信号を受信し、かつ、前記電圧検出回路に結合する出力を有する第3論理回路であって、前記電圧検出回路は、第3論理回路に結合する、第3論理回路と、
前記電圧検出回路に結合し、低電圧割り込み信号を供給する第4論理回路と、を備える請求項5に記載の集積回路。 - チャージポンプをディスエーブルする方法であって、
プログラム信号および消去信号の一方の信号に応答して第1検出イネーブル信号を供給すること、
前記電源端子の電圧が所定レベルを超える場合、前記第1検出イネーブル信号に応答して電圧有効信号を供給すること、および、
前記電圧有効信号がアサートされていないことに応答して前記チャージポンプを放電させることを含む方法。 - 前記ディスエーブルすることは、前記高電圧イネーブル信号がアサートされていないときに、高電圧イネーブル信号に応答して前記チャージポンプをディスエーブルすることとさらにみなされる請求項7に記載の方法。
- 前記高電圧イネーブル信号は、
ブロック保護信号がアサートされること、
プログラムまたは消去制御シーケンスエラーの発生、
リセット信号がアサートされること、および、
前記電圧有効信号がアサートされないこと
のうちの1つまたは複数に応答してアサートされない請求項8に記載の方法。 - 前記電源端子の電圧が前記所定の電圧より低いことに応答して、電圧ロー信号を生成すること、および、前記電圧ロー信号が生成されることに応答して、低レベル割り込み信号を生成することをさらに含む請求項7に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/946,951 | 2004-09-22 | ||
US10/946,951 US7187600B2 (en) | 2004-09-22 | 2004-09-22 | Method and apparatus for protecting an integrated circuit from erroneous operation |
PCT/US2005/031031 WO2006036443A2 (en) | 2004-09-22 | 2005-08-30 | Method and apparatus for protecting an integrated circuit from erroneous operation |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008513925A true JP2008513925A (ja) | 2008-05-01 |
JP2008513925A5 JP2008513925A5 (ja) | 2008-10-16 |
JP5101286B2 JP5101286B2 (ja) | 2012-12-19 |
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JP2007532356A Expired - Fee Related JP5101286B2 (ja) | 2004-09-22 | 2005-08-30 | 集積回路を誤った動作から保護する方法および装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7187600B2 (ja) |
JP (1) | JP5101286B2 (ja) |
KR (1) | KR101110994B1 (ja) |
CN (1) | CN100594551C (ja) |
WO (1) | WO2006036443A2 (ja) |
Cited By (3)
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JP2010272156A (ja) * | 2009-05-20 | 2010-12-02 | Renesas Electronics Corp | 半導体装置 |
JP2012014773A (ja) * | 2010-06-30 | 2012-01-19 | Renesas Electronics Corp | 不揮発性メモリ、データ処理装置、及びマイクロコンピュータ応用システム |
JP2014044786A (ja) * | 2012-08-28 | 2014-03-13 | Freescale Semiconductor Inc | ソフトプログラミングを使用する不揮発性メモリ(nvm) |
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JP2007066037A (ja) * | 2005-08-31 | 2007-03-15 | Renesas Technology Corp | 半導体集積回路 |
US7724603B2 (en) * | 2007-08-03 | 2010-05-25 | Freescale Semiconductor, Inc. | Method and circuit for preventing high voltage memory disturb |
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US7969803B2 (en) | 2008-12-16 | 2011-06-28 | Macronix International Co., Ltd. | Method and apparatus for protection of non-volatile memory in presence of out-of-specification operating voltage |
JP5328525B2 (ja) * | 2009-07-02 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN102034523B (zh) * | 2009-09-27 | 2013-09-18 | 上海宏力半导体制造有限公司 | 半导体存储装置和减少半导体存储装置芯片面积的方法 |
US8330502B2 (en) * | 2009-11-25 | 2012-12-11 | Freescale Semiconductor, Inc. | Systems and methods for detecting interference in an integrated circuit |
JP5085744B2 (ja) | 2011-01-05 | 2012-11-28 | 株式会社東芝 | 半導体記憶装置 |
TWI473099B (zh) * | 2011-12-23 | 2015-02-11 | Phison Electronics Corp | 記憶體儲存裝置、記憶體控制器與控制方法 |
US8634267B2 (en) | 2012-05-14 | 2014-01-21 | Sandisk Technologies Inc. | Flash memory chip power management for data reliability and methods thereof |
KR102081923B1 (ko) * | 2013-02-04 | 2020-02-26 | 삼성전자주식회사 | 메모리 시스템 및 메모리 컨트롤러의 동작 방법 |
TWI482161B (zh) * | 2013-08-09 | 2015-04-21 | Silicon Motion Inc | 資料儲存裝置及其電壓偵測及資料保護方法 |
CN109767804B (zh) | 2013-08-09 | 2020-12-08 | 慧荣科技股份有限公司 | 数据储存装置及其电压保护方法 |
FR3041466B1 (fr) * | 2015-09-21 | 2017-09-08 | Stmicroelectronics Rousset | Procede de controle du fonctionnement d'un dispositif de memoire de type eeprom, et dispositif correspondant |
KR20180101760A (ko) * | 2017-03-06 | 2018-09-14 | 에스케이하이닉스 주식회사 | 저장 장치, 데이터 처리 시스템 및 이의 동작 방법 |
US10747282B2 (en) * | 2018-10-17 | 2020-08-18 | Stmicroelectronics International N.V. | Test circuit for electronic device permitting interface control between two supply stacks in a production test of the electronic device |
TWI682397B (zh) * | 2018-12-12 | 2020-01-11 | 新唐科技股份有限公司 | 資料處理系統與資料處理方法 |
US10586600B1 (en) * | 2019-01-28 | 2020-03-10 | Micron Technology, Inc. | High-voltage shifter with reduced transistor degradation |
CN113906507A (zh) * | 2019-05-31 | 2022-01-07 | 美光科技公司 | 用于闪存阵列的智能电荷泵架构 |
US10877541B1 (en) | 2019-12-30 | 2020-12-29 | Micron Technology, Inc. | Power delivery timing for memory |
KR20220148551A (ko) | 2021-04-29 | 2022-11-07 | 삼성전자주식회사 | 스토리지 장치 및 메모리 시스템 |
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- 2005-08-30 CN CN200580031462A patent/CN100594551C/zh active Active
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Also Published As
Publication number | Publication date |
---|---|
WO2006036443A2 (en) | 2006-04-06 |
JP5101286B2 (ja) | 2012-12-19 |
CN100594551C (zh) | 2010-03-17 |
US7187600B2 (en) | 2007-03-06 |
KR20070054673A (ko) | 2007-05-29 |
KR101110994B1 (ko) | 2012-02-17 |
CN101023491A (zh) | 2007-08-22 |
WO2006036443A3 (en) | 2006-10-12 |
US20060062070A1 (en) | 2006-03-23 |
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