JP2008512875A5 - - Google Patents

Download PDF

Info

Publication number
JP2008512875A5
JP2008512875A5 JP2007531406A JP2007531406A JP2008512875A5 JP 2008512875 A5 JP2008512875 A5 JP 2008512875A5 JP 2007531406 A JP2007531406 A JP 2007531406A JP 2007531406 A JP2007531406 A JP 2007531406A JP 2008512875 A5 JP2008512875 A5 JP 2008512875A5
Authority
JP
Japan
Prior art keywords
magnetic member
magnetic
etching
layer
insulating tunnel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007531406A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008512875A (ja
JP5261629B2 (ja
Filing date
Publication date
Priority claimed from US10/937,660 external-priority patent/US7169623B2/en
Application filed filed Critical
Publication of JP2008512875A publication Critical patent/JP2008512875A/ja
Publication of JP2008512875A5 publication Critical patent/JP2008512875A5/ja
Application granted granted Critical
Publication of JP5261629B2 publication Critical patent/JP5261629B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

JP2007531406A 2004-09-09 2005-09-09 ストップ−オン−アルミニウム処理を含むウェーハ処理のためのシステム及び方法 Expired - Lifetime JP5261629B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/937,660 2004-09-09
US10/937,660 US7169623B2 (en) 2004-09-09 2004-09-09 System and method for processing a wafer including stop-on-aluminum processing
PCT/US2005/032303 WO2006029374A2 (en) 2004-09-09 2005-09-09 System and method for processing a wafer including stop-on-aluminum processing

Publications (3)

Publication Number Publication Date
JP2008512875A JP2008512875A (ja) 2008-04-24
JP2008512875A5 true JP2008512875A5 (enExample) 2008-10-16
JP5261629B2 JP5261629B2 (ja) 2013-08-14

Family

ID=35996768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007531406A Expired - Lifetime JP5261629B2 (ja) 2004-09-09 2005-09-09 ストップ−オン−アルミニウム処理を含むウェーハ処理のためのシステム及び方法

Country Status (3)

Country Link
US (2) US7169623B2 (enExample)
JP (1) JP5261629B2 (enExample)
WO (1) WO2006029374A2 (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7374952B2 (en) * 2004-06-17 2008-05-20 Infineon Technologies Ag Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof
US7368299B2 (en) * 2004-07-14 2008-05-06 Infineon Technologies Ag MTJ patterning using free layer wet etching and lift off techniques
US8193096B2 (en) 2004-12-13 2012-06-05 Novellus Systems, Inc. High dose implantation strip (HDIS) in H2 base chemistry
US8582252B2 (en) 2005-11-02 2013-11-12 Seagate Technology Llc Magnetic layer with grain refining agent
US7445943B2 (en) * 2006-10-19 2008-11-04 Everspin Technologies, Inc. Magnetic tunnel junction memory and method with etch-stop layer
US7618894B2 (en) * 2007-07-26 2009-11-17 Unity Semiconductor Corporation Multi-step selective etching for cross-point memory
RU2367057C2 (ru) * 2007-10-31 2009-09-10 Государственное образовательное учреждение высшего профессионального образования "Московский Инженерно-Физический Институт (государственный университет)" Способ формирования структур магнитных туннельных переходов для магниторезистивной магнитной памяти произвольного доступа и структура магнитного туннельного перехода для магниторезистивной магнитной памяти произвольного доступа (варианты)
RU2394304C2 (ru) * 2007-12-26 2010-07-10 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Национальный исследовательский ядерный университет МИФИ" (НИЯУ МИФИ) Способ формирования структуры магнитного туннельного перехода на основе наноразмерных структур металл-изолятор-металл и структура магнитного туннельного перехода на основе наноразмерных структур металл-изолятор-металл (варианты)
US7880209B2 (en) * 2008-10-09 2011-02-01 Seagate Technology Llc MRAM cells including coupled free ferromagnetic layers for stabilization
KR101527533B1 (ko) * 2009-01-09 2015-06-10 삼성전자주식회사 자기 메모리 소자의 형성방법
JP5058206B2 (ja) * 2009-04-27 2012-10-24 株式会社東芝 磁気抵抗素子の製造方法
JP2011060918A (ja) * 2009-09-08 2011-03-24 Nippon Hoso Kyokai <Nhk> スピン注入磁化反転素子、磁気ランダムアクセスメモリ、光変調器、表示装置、ホログラフィ装置、ホログラム記録装置および光変調器の製造方法
US20110143548A1 (en) 2009-12-11 2011-06-16 David Cheung Ultra low silicon loss high dose implant strip
JP2012099589A (ja) * 2010-11-01 2012-05-24 Hitachi High-Technologies Corp プラズマ処理方法
US8962493B2 (en) * 2010-12-13 2015-02-24 Crocus Technology Inc. Magnetic random access memory cells having improved size and shape characteristics
US9613825B2 (en) * 2011-08-26 2017-04-04 Novellus Systems, Inc. Photoresist strip processes for improved device integrity
US8748197B2 (en) * 2012-03-14 2014-06-10 Headway Technologies, Inc. Reverse partial etching scheme for magnetic device applications
US20140003118A1 (en) * 2012-07-02 2014-01-02 International Business Machines Corporation Magnetic tunnel junction self-alignment in magnetic domain wall shift register memory devices
US9466788B2 (en) * 2014-02-18 2016-10-11 Everspin Technologies, Inc. Top electrode etch in a magnetoresistive device and devices manufactured using same
US9343661B2 (en) 2014-02-18 2016-05-17 Everspin Technologies, Inc. Non-reactive photoresist removal and spacer layer optimization in a magnetoresistive device
US9514954B2 (en) 2014-06-10 2016-12-06 Lam Research Corporation Peroxide-vapor treatment for enhancing photoresist-strip performance and modifying organic films
JP6574486B2 (ja) * 2015-02-15 2019-09-11 エーシーエム リサーチ （シャンハイ） インコーポレーテッド 金属層形成方法
US9525125B1 (en) * 2015-08-20 2016-12-20 International Business Machines Corporation Linear magnetoresistive random access memory device with a self-aligned contact above MRAM nanowire
US11043251B2 (en) 2018-11-30 2021-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Magnetic tunnel junction device and method of forming same
CN112563412B (zh) * 2019-09-25 2023-06-23 浙江驰拓科技有限公司 磁性隧道结刻蚀方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ID28920A (id) * 1999-07-22 2001-07-12 Koninkl Philips Electronics Nv Metode pembuatan peranti sambungan saluran magnetik
JP4809991B2 (ja) * 2001-04-17 2011-11-09 キヤノン株式会社 トンネル磁気抵抗素子の加工方法
US6682943B2 (en) 2001-04-27 2004-01-27 Micron Technology, Inc. Method for forming minimally spaced MRAM structures
JP2003078185A (ja) * 2001-09-03 2003-03-14 Nec Corp 強磁性トンネル接合構造及びその製造方法並びに該強磁性トンネル接合を用いた磁気メモリ
JP3854839B2 (ja) * 2001-10-02 2006-12-06 キヤノン株式会社 磁気抵抗素子を用いた不揮発固体メモリ
US6815248B2 (en) 2002-04-18 2004-11-09 Infineon Technologies Ag Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed layer in MRAM processing
JP2003324187A (ja) * 2002-05-01 2003-11-14 Sony Corp 磁気メモリ装置の製造方法および磁気メモリ装置
JP2004128229A (ja) * 2002-10-02 2004-04-22 Nec Corp 磁性メモリ及びその製造方法
JP2004214459A (ja) * 2003-01-06 2004-07-29 Sony Corp 不揮発性磁気メモリ装置及びその製造方法
US6984529B2 (en) * 2003-09-10 2006-01-10 Infineon Technologies Ag Fabrication process for a magnetic tunnel junction device

Similar Documents

Publication Publication Date Title
JP2008512875A5 (enExample)
US10847715B2 (en) Magnetoresistive device and method of manufacturing same
JP2006524436A5 (enExample)
JP5296672B2 (ja) ストレッサを備える構造及びその製造方法
JP2008517468A5 (enExample)
JP2015216360A5 (enExample)
US9875965B2 (en) Semiconductor device
JP2005535119A5 (enExample)
JP2009505424A5 (enExample)
JP5261629B2 (ja) ストップ−オン−アルミニウム処理を含むウェーハ処理のためのシステム及び方法
WO2004095515A8 (en) Methods for contracting conducting layers overlying magnetoelectronic elements of mram devices
JP2018037656A5 (enExample)
JP2011505697A5 (enExample)
JP2016066793A5 (enExample)
CN103794717A (zh) 一种包含介电层的嵌入型磁隧道结器件的制造方法
KR20190130169A (ko) 미리 패터닝된 시드 층을 가진 mtj 디바이스 프로세스/집적 방법
CN110546777A (zh) 用于物理蚀刻制程的减少分流的装置的后处理
JP2006013136A5 (enExample)
CN104813402B (zh) 用于hdd位元图案化介质图案转印的图案强化
TWI550693B (zh) 圖案化非依電性記憶體（ｎｖｍ）之閘極堆疊並同時在非ｎｖｍ區域中進行蝕刻之技術
KR20150112979A (ko) 자기저항 디바이스를 제조하는 방법
JP2006165032A (ja) エッチング方法および装置
JP2003534659A (ja) 半導体装置の反射防止膜をドライエッチングにより除去する方法
TW518688B (en) Etching process of dielectric layer
JP2005303032A5 (enExample)