JP2018037656A5 - - Google Patents

Download PDF

Info

Publication number
JP2018037656A5
JP2018037656A5 JP2017163358A JP2017163358A JP2018037656A5 JP 2018037656 A5 JP2018037656 A5 JP 2018037656A5 JP 2017163358 A JP2017163358 A JP 2017163358A JP 2017163358 A JP2017163358 A JP 2017163358A JP 2018037656 A5 JP2018037656 A5 JP 2018037656A5
Authority
JP
Japan
Prior art keywords
spacer
passivation
etching
nitride
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2017163358A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018037656A (ja
JP6779846B2 (ja
Filing date
Publication date
Priority claimed from US15/486,928 external-priority patent/US10453686B2/en
Application filed filed Critical
Publication of JP2018037656A publication Critical patent/JP2018037656A/ja
Publication of JP2018037656A5 publication Critical patent/JP2018037656A5/ja
Application granted granted Critical
Publication of JP6779846B2 publication Critical patent/JP6779846B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2017163358A 2016-08-31 2017-08-28 セルフアライン式マルチパターニングのためのその場スペーサ再整形方法及びシステム Active JP6779846B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662382110P 2016-08-31 2016-08-31
US62/382,110 2016-08-31
US15/486,928 2017-04-13
US15/486,928 US10453686B2 (en) 2016-08-31 2017-04-13 In-situ spacer reshaping for self-aligned multi-patterning methods and systems

Publications (3)

Publication Number Publication Date
JP2018037656A JP2018037656A (ja) 2018-03-08
JP2018037656A5 true JP2018037656A5 (enExample) 2020-10-01
JP6779846B2 JP6779846B2 (ja) 2020-11-04

Family

ID=61243201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017163358A Active JP6779846B2 (ja) 2016-08-31 2017-08-28 セルフアライン式マルチパターニングのためのその場スペーサ再整形方法及びシステム

Country Status (5)

Country Link
US (1) US10453686B2 (enExample)
JP (1) JP6779846B2 (enExample)
KR (1) KR102250213B1 (enExample)
CN (1) CN107799458B (enExample)
TW (1) TWI728178B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10340149B2 (en) * 2017-09-05 2019-07-02 Nanya Technology Corporation Method of forming dense hole patterns of semiconductor devices
US10163635B1 (en) * 2017-10-30 2018-12-25 Globalfoundries Inc. Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method
US10439047B2 (en) * 2018-02-14 2019-10-08 Applied Materials, Inc. Methods for etch mask and fin structure formation
US10340136B1 (en) * 2018-07-19 2019-07-02 Lam Research Corporation Minimization of carbon loss in ALD SiO2 deposition on hardmask films
KR102939729B1 (ko) 2018-11-16 2026-03-13 램 리써치 코포레이션 기포 결함 감소
US11551930B2 (en) * 2018-12-12 2023-01-10 Tokyo Electron Limited Methods to reshape spacer profiles in self-aligned multiple patterning
JP7145819B2 (ja) * 2019-06-24 2022-10-03 東京エレクトロン株式会社 エッチング方法
TWI730821B (zh) * 2020-06-22 2021-06-11 力晶積成電子製造股份有限公司 多重圖案化方法
US12451353B2 (en) 2022-08-03 2025-10-21 Tokyo Electron Limited Double hardmasks for self-aligned multi-patterning processes

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7291560B2 (en) * 2005-08-01 2007-11-06 Infineon Technologies Ag Method of production pitch fractionizations in semiconductor technology
US7265059B2 (en) * 2005-09-30 2007-09-04 Freescale Semiconductor, Inc. Multiple fin formation
KR20080059429A (ko) * 2005-10-05 2008-06-27 어드밴스드 테크놀러지 머티리얼즈, 인코포레이티드 게이트 스페이서 산화물 재료를 선택적으로 에칭하기 위한조성물 및 방법
US8298949B2 (en) * 2009-01-07 2012-10-30 Lam Research Corporation Profile and CD uniformity control by plasma oxidation treatment
CN102428544B (zh) * 2009-05-20 2014-10-29 株式会社东芝 凹凸图案形成方法
KR101105508B1 (ko) * 2009-12-30 2012-01-13 주식회사 하이닉스반도체 반도체 메모리 소자의 제조 방법
US8962484B2 (en) * 2011-12-16 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming pattern for semiconductor device
KR101644732B1 (ko) * 2012-04-11 2016-08-01 도쿄엘렉트론가부시키가이샤 Finfet 방식용 게이트 스페이서 프로파일, 핀 손실 및 하드 마스크 손실 개선을 위한 종횡비 종속 성막
WO2014197324A1 (en) 2013-06-04 2014-12-11 Tokyo Electron Limited Mitigation of asymmetrical profile in self aligned patterning etch
JP6026375B2 (ja) * 2013-09-02 2016-11-16 株式会社東芝 半導体装置の製造方法
US9165770B2 (en) * 2013-09-26 2015-10-20 GlobalFoundries, Inc. Methods for fabricating integrated circuits using improved masks
US9287262B2 (en) * 2013-10-10 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Passivated and faceted for fin field effect transistor
US9184058B2 (en) * 2013-12-23 2015-11-10 Micron Technology, Inc. Methods of forming patterns by using a brush layer and masks
US9293341B2 (en) 2014-03-13 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming patterns using multiple lithography processes
US9633907B2 (en) * 2014-05-28 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned nanowire formation using double patterning
US9484201B2 (en) * 2015-02-23 2016-11-01 International Business Machines Corporation Epitaxial silicon germanium fin formation using sacrificial silicon fin templates
US9530646B2 (en) * 2015-02-24 2016-12-27 United Microelectronics Corp. Method of forming a semiconductor structure
US9640409B1 (en) * 2016-02-02 2017-05-02 Lam Research Corporation Self-limited planarization of hardmask

Similar Documents

Publication Publication Date Title
JP2018037656A5 (enExample)
TWI579892B (zh) 用以形成具有多膜層的間隔壁之蝕刻方法
CN101271922B (zh) 晶体管及其制造方法
JP7175237B2 (ja) 酸化物の原子層エッチングの方法
CN105719954B (zh) 半导体结构的形成方法
TWI534889B (zh) 減輕自我對準圖案化蝕刻中之非對稱輪廓
CN107359111A (zh) 一种自对准双重图形化的方法
JP2012516555A5 (enExample)
CN105977141A (zh) 一种自对准双重图形化的方法
CN105632885B (zh) 半导体结构的形成方法
WO2011102140A1 (ja) 半導体装置の製造方法
CN108574010B (zh) 半导体结构及其形成方法
CN109427559A (zh) 半导体器件及其形成方法
CN108321090A (zh) 半导体器件及其形成方法
CN107437497B (zh) 半导体器件的形成方法
CN103928304B (zh) 一种多晶硅上小尺寸图形结构的制备方法
CN104064474B (zh) 双重图形化鳍式晶体管的鳍结构制造方法
CN103681274A (zh) 半导体器件制造方法
KR20190068464A (ko) 기판을 멀티 패터닝하는 기술
CN110690112B (zh) 利用反向间距加倍工艺形成表面平坦化结构及方法
CN103456624A (zh) 过孔刻蚀方法
CN105304474A (zh) 一种多重图形化掩膜层的形成方法
CN103928313B (zh) 一种小尺寸图形的制作方法
CN110556338A (zh) 半导体器件及其形成方法
CN112563200B (zh) 半导体器件及其形成方法