CN107799458B - 自对准多重图案化的原位间隔件整形的方法和系统 - Google Patents

自对准多重图案化的原位间隔件整形的方法和系统 Download PDF

Info

Publication number
CN107799458B
CN107799458B CN201710763389.9A CN201710763389A CN107799458B CN 107799458 B CN107799458 B CN 107799458B CN 201710763389 A CN201710763389 A CN 201710763389A CN 107799458 B CN107799458 B CN 107799458B
Authority
CN
China
Prior art keywords
spacer
substrate
passivation
etching
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710763389.9A
Other languages
English (en)
Chinese (zh)
Other versions
CN107799458A (zh
Inventor
刘志方
安热利克·雷利
高明辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of CN107799458A publication Critical patent/CN107799458A/zh
Application granted granted Critical
Publication of CN107799458B publication Critical patent/CN107799458B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H10P72/0418—Apparatus for fluid treatment for etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment

Landscapes

  • Drying Of Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CN201710763389.9A 2016-08-31 2017-08-30 自对准多重图案化的原位间隔件整形的方法和系统 Active CN107799458B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662382110P 2016-08-31 2016-08-31
US62/382,110 2016-08-31
US15/486,928 2017-04-13
US15/486,928 US10453686B2 (en) 2016-08-31 2017-04-13 In-situ spacer reshaping for self-aligned multi-patterning methods and systems

Publications (2)

Publication Number Publication Date
CN107799458A CN107799458A (zh) 2018-03-13
CN107799458B true CN107799458B (zh) 2023-12-08

Family

ID=61243201

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710763389.9A Active CN107799458B (zh) 2016-08-31 2017-08-30 自对准多重图案化的原位间隔件整形的方法和系统

Country Status (5)

Country Link
US (1) US10453686B2 (enExample)
JP (1) JP6779846B2 (enExample)
KR (1) KR102250213B1 (enExample)
CN (1) CN107799458B (enExample)
TW (1) TWI728178B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10340149B2 (en) * 2017-09-05 2019-07-02 Nanya Technology Corporation Method of forming dense hole patterns of semiconductor devices
US10163635B1 (en) * 2017-10-30 2018-12-25 Globalfoundries Inc. Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method
US10439047B2 (en) * 2018-02-14 2019-10-08 Applied Materials, Inc. Methods for etch mask and fin structure formation
US10340136B1 (en) * 2018-07-19 2019-07-02 Lam Research Corporation Minimization of carbon loss in ALD SiO2 deposition on hardmask films
KR102939729B1 (ko) 2018-11-16 2026-03-13 램 리써치 코포레이션 기포 결함 감소
US11551930B2 (en) * 2018-12-12 2023-01-10 Tokyo Electron Limited Methods to reshape spacer profiles in self-aligned multiple patterning
JP7145819B2 (ja) * 2019-06-24 2022-10-03 東京エレクトロン株式会社 エッチング方法
TWI730821B (zh) * 2020-06-22 2021-06-11 力晶積成電子製造股份有限公司 多重圖案化方法
US12451353B2 (en) 2022-08-03 2025-10-21 Tokyo Electron Limited Double hardmasks for self-aligned multi-patterning processes

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1909205A (zh) * 2005-08-01 2007-02-07 奇梦达股份公司 半导体技术中产生间距细分的方法
CN102136416A (zh) * 2009-12-30 2011-07-27 海力士半导体有限公司 制造半导体器件的方法
CN102272902A (zh) * 2009-01-07 2011-12-07 朗姆研究公司 通过等离子体氧化处理的轮廓和cd均匀性控制
CN102428544A (zh) * 2009-05-20 2012-04-25 株式会社东芝 凹凸图案形成方法
JP2015050358A (ja) * 2013-09-02 2015-03-16 株式会社東芝 半導体装置の製造方法
CN104576733A (zh) * 2013-10-10 2015-04-29 台湾积体电路制造股份有限公司 鳍式场效应晶体管的钝化和晶面形成
JP2015149473A (ja) * 2013-12-23 2015-08-20 マイクロン テクノロジー， インク． パターン形成方法
CN105140100A (zh) * 2014-05-28 2015-12-09 台湾积体电路制造股份有限公司 使用双重图案化的自对准纳米线的形成
CN107039265A (zh) * 2016-02-02 2017-08-11 朗姆研究公司 硬掩膜的自限性平坦化

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7265059B2 (en) * 2005-09-30 2007-09-04 Freescale Semiconductor, Inc. Multiple fin formation
KR20080059429A (ko) * 2005-10-05 2008-06-27 어드밴스드 테크놀러지 머티리얼즈, 인코포레이티드 게이트 스페이서 산화물 재료를 선택적으로 에칭하기 위한조성물 및 방법
US8962484B2 (en) * 2011-12-16 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming pattern for semiconductor device
KR101644732B1 (ko) * 2012-04-11 2016-08-01 도쿄엘렉트론가부시키가이샤 Finfet 방식용 게이트 스페이서 프로파일, 핀 손실 및 하드 마스크 손실 개선을 위한 종횡비 종속 성막
WO2014197324A1 (en) 2013-06-04 2014-12-11 Tokyo Electron Limited Mitigation of asymmetrical profile in self aligned patterning etch
US9165770B2 (en) * 2013-09-26 2015-10-20 GlobalFoundries, Inc. Methods for fabricating integrated circuits using improved masks
US9293341B2 (en) 2014-03-13 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming patterns using multiple lithography processes
US9484201B2 (en) * 2015-02-23 2016-11-01 International Business Machines Corporation Epitaxial silicon germanium fin formation using sacrificial silicon fin templates
US9530646B2 (en) * 2015-02-24 2016-12-27 United Microelectronics Corp. Method of forming a semiconductor structure

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1909205A (zh) * 2005-08-01 2007-02-07 奇梦达股份公司 半导体技术中产生间距细分的方法
CN102272902A (zh) * 2009-01-07 2011-12-07 朗姆研究公司 通过等离子体氧化处理的轮廓和cd均匀性控制
CN102428544A (zh) * 2009-05-20 2012-04-25 株式会社东芝 凹凸图案形成方法
CN102136416A (zh) * 2009-12-30 2011-07-27 海力士半导体有限公司 制造半导体器件的方法
JP2015050358A (ja) * 2013-09-02 2015-03-16 株式会社東芝 半導体装置の製造方法
CN104576733A (zh) * 2013-10-10 2015-04-29 台湾积体电路制造股份有限公司 鳍式场效应晶体管的钝化和晶面形成
JP2015149473A (ja) * 2013-12-23 2015-08-20 マイクロン テクノロジー， インク． パターン形成方法
CN105140100A (zh) * 2014-05-28 2015-12-09 台湾积体电路制造股份有限公司 使用双重图案化的自对准纳米线的形成
CN107039265A (zh) * 2016-02-02 2017-08-11 朗姆研究公司 硬掩膜的自限性平坦化

Also Published As

Publication number Publication date
JP2018037656A (ja) 2018-03-08
TWI728178B (zh) 2021-05-21
CN107799458A (zh) 2018-03-13
KR102250213B1 (ko) 2021-05-07
US20180061640A1 (en) 2018-03-01
US10453686B2 (en) 2019-10-22
JP6779846B2 (ja) 2020-11-04
TW201820389A (zh) 2018-06-01
KR20180025273A (ko) 2018-03-08

Similar Documents

Publication Publication Date Title
CN107799458B (zh) 自对准多重图案化的原位间隔件整形的方法和系统
KR102445013B1 (ko) 하드 마스크들을 사용하지 않고서 자기 정렬 패터닝 방식들에서 패턴 밀도를 증가시키는 방법
US9443731B1 (en) Material processing to achieve sub-10nm patterning
TWI492297B (zh) 電漿蝕刻方法、半導體裝置之製造方法、及電漿蝕刻裝置
US20170358450A1 (en) Organic Mandrel Protection Process
KR102328025B1 (ko) 서브-해상도 스케일들로 상이한 임계 치수들을 패터닝하기 위한 방법
KR102460795B1 (ko) 낮은 종횡비 적층물의 패터닝을 위한 방법 및 시스템
US10170329B2 (en) Spacer formation for self-aligned multi-patterning technique
US10790154B2 (en) Method of line cut by multi-color patterning technique
KR102349721B1 (ko) 탄탈 질화물(TaN)층에서 피처를 패터닝하기 위한 시스템 및 방법
US10937664B2 (en) Surface modification process
US10811273B2 (en) Methods of surface restoration for nitride etching

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant