TWI728178B - 用於自對準多重圖案化方法與系統之原位間隔件再成形 - Google Patents

用於自對準多重圖案化方法與系統之原位間隔件再成形 Download PDF

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Publication number
TWI728178B
TWI728178B TW106129280A TW106129280A TWI728178B TW I728178 B TWI728178 B TW I728178B TW 106129280 A TW106129280 A TW 106129280A TW 106129280 A TW106129280 A TW 106129280A TW I728178 B TWI728178 B TW I728178B
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Taiwan
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substrate
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TW106129280A
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Chinese (zh)
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TW201820389A (zh
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劉志方
安潔莉 萊利
高明輝
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日商東京威力科創股份有限公司
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326Deposition processes
    • H10P14/6328Deposition from the gas or vapour phase
    • H10P14/6334Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04Apparatus for manufacture or treatment
    • H10P72/0402Apparatus for fluid treatment
    • H10P72/0418Apparatus for fluid treatment for etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment

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  • Drying Of Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW106129280A 2016-08-31 2017-08-29 用於自對準多重圖案化方法與系統之原位間隔件再成形 TWI728178B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662382110P 2016-08-31 2016-08-31
US62/382,110 2016-08-31
US15/486,928 2017-04-13
US15/486,928 US10453686B2 (en) 2016-08-31 2017-04-13 In-situ spacer reshaping for self-aligned multi-patterning methods and systems

Publications (2)

Publication Number Publication Date
TW201820389A TW201820389A (zh) 2018-06-01
TWI728178B true TWI728178B (zh) 2021-05-21

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TW106129280A TWI728178B (zh) 2016-08-31 2017-08-29 用於自對準多重圖案化方法與系統之原位間隔件再成形

Country Status (5)

Country Link
US (1) US10453686B2 (enExample)
JP (1) JP6779846B2 (enExample)
KR (1) KR102250213B1 (enExample)
CN (1) CN107799458B (enExample)
TW (1) TWI728178B (enExample)

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US10340149B2 (en) * 2017-09-05 2019-07-02 Nanya Technology Corporation Method of forming dense hole patterns of semiconductor devices
US10163635B1 (en) * 2017-10-30 2018-12-25 Globalfoundries Inc. Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method
US10439047B2 (en) * 2018-02-14 2019-10-08 Applied Materials, Inc. Methods for etch mask and fin structure formation
US10340136B1 (en) * 2018-07-19 2019-07-02 Lam Research Corporation Minimization of carbon loss in ALD SiO2 deposition on hardmask films
KR102939729B1 (ko) 2018-11-16 2026-03-13 램 리써치 코포레이션 기포 결함 감소
US11551930B2 (en) * 2018-12-12 2023-01-10 Tokyo Electron Limited Methods to reshape spacer profiles in self-aligned multiple patterning
JP7145819B2 (ja) * 2019-06-24 2022-10-03 東京エレクトロン株式会社 エッチング方法
TWI730821B (zh) * 2020-06-22 2021-06-11 力晶積成電子製造股份有限公司 多重圖案化方法
US12451353B2 (en) 2022-08-03 2025-10-21 Tokyo Electron Limited Double hardmasks for self-aligned multi-patterning processes

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TW200726826A (en) * 2005-10-05 2007-07-16 Advanced Tech Materials Composition and method for selectively etching gate spacer oxide material
TW201405668A (zh) * 2012-04-11 2014-02-01 東京威力科創股份有限公司 用於鰭式場效電晶體之深寬比依存的沉積以改善閘極間隔物輪廓、鰭損耗及硬遮罩損耗
US20160247883A1 (en) * 2015-02-23 2016-08-25 International Business Machines Corporation Epitaxial silicon germanium fin formation using sacrificial silicon fin templates

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US7291560B2 (en) * 2005-08-01 2007-11-06 Infineon Technologies Ag Method of production pitch fractionizations in semiconductor technology
US7265059B2 (en) * 2005-09-30 2007-09-04 Freescale Semiconductor, Inc. Multiple fin formation
US8298949B2 (en) * 2009-01-07 2012-10-30 Lam Research Corporation Profile and CD uniformity control by plasma oxidation treatment
CN102428544B (zh) * 2009-05-20 2014-10-29 株式会社东芝 凹凸图案形成方法
KR101105508B1 (ko) * 2009-12-30 2012-01-13 주식회사 하이닉스반도체 반도체 메모리 소자의 제조 방법
US8962484B2 (en) * 2011-12-16 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming pattern for semiconductor device
WO2014197324A1 (en) 2013-06-04 2014-12-11 Tokyo Electron Limited Mitigation of asymmetrical profile in self aligned patterning etch
JP6026375B2 (ja) * 2013-09-02 2016-11-16 株式会社東芝 半導体装置の製造方法
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TW200726826A (en) * 2005-10-05 2007-07-16 Advanced Tech Materials Composition and method for selectively etching gate spacer oxide material
TW201405668A (zh) * 2012-04-11 2014-02-01 東京威力科創股份有限公司 用於鰭式場效電晶體之深寬比依存的沉積以改善閘極間隔物輪廓、鰭損耗及硬遮罩損耗
US20160247883A1 (en) * 2015-02-23 2016-08-25 International Business Machines Corporation Epitaxial silicon germanium fin formation using sacrificial silicon fin templates

Also Published As

Publication number Publication date
JP2018037656A (ja) 2018-03-08
CN107799458A (zh) 2018-03-13
KR102250213B1 (ko) 2021-05-07
US20180061640A1 (en) 2018-03-01
US10453686B2 (en) 2019-10-22
JP6779846B2 (ja) 2020-11-04
TW201820389A (zh) 2018-06-01
KR20180025273A (ko) 2018-03-08
CN107799458B (zh) 2023-12-08

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