JP2008060256A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2008060256A JP2008060256A JP2006234061A JP2006234061A JP2008060256A JP 2008060256 A JP2008060256 A JP 2008060256A JP 2006234061 A JP2006234061 A JP 2006234061A JP 2006234061 A JP2006234061 A JP 2006234061A JP 2008060256 A JP2008060256 A JP 2008060256A
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- Prior art keywords
- chip
- die pad
- semiconductor device
- electrode
- sealing body
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
【解決手段】第1チップ21を第1ダイパッド31上に搭載し、併せて第2チップ22も第2ダイパッド32上に搭載する。第1ダイパッド31と、第2ダイパッド32とは、封止体40の第1辺41、第2辺42に平行に分割構成する。その結果、第1チップ21からの出力用ピン51と、駆動用回路の制御用ピン52が、反対方向から突出させることができ、実装時の配線レイアウトを最小ルートに設定することができる。
【選択図】図1
Description
図1は、本発明の一実施の形態の半導体装置の全体構成の一例を模式的に示す平面図である。図2(a)は図1のA−A線で切断した様子を模式的に示す断面図であり、(b)はB−B線で切断した様子を模式的に示す断面図であり、(c)は板状電極の構成を示す断面図である。図3は、ダイパッドの様子を模式的に示す断面図である。図4は、ダイパッド間の離間距離を示す断面説明図である。図5(a)はダイパッド部の厚さがリードより厚い構成のリードフレームを用いて図1に示す構成の半導体装置を形成した場合のA−A線での切断の様子を模式的に示す断面図であり、(b)はB−B線での切断の様子を示す断面図である。図6は、本発明の半導体装置で使用する半導体チップの一例を示した断面図である。
本実施の形態では、前記実施の形態1で述べたように、一枚構成のダイパッドでも第1端面31aの切れ込みを深く形成しておくことにより、ダイパッドを分割構成した場合に使用されるモールド金型で、モールドが行える場合について説明する。
本実施の形態では、前記実施の形態2と同様に、ダイパッド30が分割構成されていない他の例について説明する。図12(a)に示すように、ダイパッド30上に、例えばMOSFETであるチップ21aが搭載された場合を挙げることができる。かかる場合でも、前記金型封止で述べたように、ダイパッド30の第1端面31aが深く形成されているため、モールド時にレジン漏れを防止して、十分な精度で封止体40を形成することができる。
本実施の形態では、前記実施の形態2と同様に、ダイパッド30に第1端面31aが形成されて、かかる第1端面31aが封止体40の内部に内包されている半導体装置10の他の例を挙げる。かかる場合には、図13(a)に示すように、例えばダイパッド30上に2個のNチャンネルMOSFETであるチップ21aと、ダイオードであるチップ21bが搭載されている。
本実施の形態では、前記実施の形態1で説明した半導体装置10の実装形態について説明する。半導体装置10は、図14の回路ブロック図に示すように、コントローラIC80と電気的に接続されて使用される。
前記実施の形態で述べた構成の半導体装置10においては、実装に際して、電源用の配線と、負荷用の配線とは、例えば、BUS−BARと呼ばれるような複数個の半導体装置10を一括して処理できるような配線レイアウトが採用される場合がある。
前記実施の形態6では、前記実施の形態1で説明した半導体装置10を用いた場合のBUS−BAR配線における優位性を述べたが、BUS−BAR配線を利用して半導体装置10の放熱性の向上を図ることもできる。
本実施の形態では、前記実施の形態1で説明した半導体装置10の板状電極61の変形例を示したものである。
前記実施の形態1で説明した半導体装置10の製造方法では、例えば、第1チップ21、第2チップ22を、第1ダイパッド31、第2ダイパッド32上にそれぞれダイボンディングする際に、半田ペーストを用いる場合について説明した。しかし、かかるダイボンド材には、半田ペーストの他に、Agペースト等のように他のペーストを用いても製造することができる。
本実施の形態では、前記実施の形態1で説明した半導体装置10の変形例について説明する。
本実施の形態では、前記実施の形態1で説明した半導体装置10の変形例について説明する。
本実施の形態では、前記実施の形態1で説明した半導体装置10の変形例について説明する。
本実施の形態では、前記実施の形態1で説明した半導体装置10の変形例について説明する。
本実施の形態では、前記実施の形態1で説明した半導体装置10の変形例について説明する。
本実施の形態では、前記実施の形態1で説明した半導体装置10の変形例について説明する。
前記実施の形態では、いずれの場合にも、ダイパッドのチップ搭載面と、チップと電気的接続がなされるリードの接続面とが、異なる高さの状態でモールドされている場合を例に挙げて説明した。
10a 半導体装置
20 半導体チップ(チップ)
21 第1チップ
21a チップ(パワートランジスタ)
21b チップ
21c チップ
22 第2チップ
22a 駆動用回路
22b チップ
22c チップ
30 ダイパッド
30a 端部
31 第1ダイパッド
31a 第1端面
31s 搭載面
32 第2ダイパッド
32s 搭載面
33 露出部分
40 封止体
41 第1辺
42 第2辺
43 第3辺
50 リードフレーム
50a リード
50b リード
50c リード
50d リード
51 出力用ピン
51s 接続面
52 制御用ピン
52s 接続面
61 板状電極
61a チップ側電極接続部
61b リード用電極接続部
61c 連結部
61d 基部
62 板状電極
62a 凹部
63 板状電極
64 板状電極
65 板状電極
65a チップ側電極接続部
65b リード用電極接続部
65c 連結部
70 ワイヤ
70a ワイヤ
70b ワイヤ
70c ワイヤ
70d ワイヤ
70e ワイヤ
70A ワイヤ
70B ワイヤ
70C ワイヤ
70D ワイヤ
70E ワイヤ
70F ワイヤ
70G ワイヤ
70H ワイヤ
80 コントローラIC
100 電源用BUS−BAR
200 負荷用BUS−BAR
201 基板(半導体基板)
201A n+型単結晶シリコン基板
201B n−型単結晶シリコン層
201C 基板(半導体基板)
201D p++型単結晶シリコン基板
201E n+型単結晶シリコン層
203 酸化シリコン膜
205 p型ウエル
206 フィールド絶縁膜
207 p−型半導体領域
208 n+型半導体領域
210 溝
211 熱酸化膜
212 ゲート電極
213 多結晶シリコンパターン
216 絶縁膜
217 コンタクト溝
218 コンタクト溝
219 コンタクト溝
220 p+型半導体領域
222 バリア導体膜
223 シード膜
225 導電性膜
226 配線
227 配線
228 配線
231 窒化シリコン膜
232 ポリイミド樹脂膜
233 開口部
236 バンプ下地膜
237 Ti膜
238 Ni膜
239 Au膜
240 引き出し電極
241 バンプ電極
a Gate端子
b Cathode端子
c Anode端子
d SenseSource端子
e SenseGND端子
A VB端子
B Vin端子
C Diag端子
D C1端子
E C2端子
F VCP端子
G VDDTEST端子
H GND端子
h1 高さ
h2 高さ
h3 高さ
Claims (11)
- パワートランジスタを含む第1チップと、
前記パワートランジスタを駆動する駆動用回路含む第2チップと
前記第1チップが搭載された第1ダイパッドと、
前記第2チップが搭載された第2ダイパッドと、
前記第1ダイパッド、前記第2ダイパッドの一部、及び前記第1チップ、前記第2チップを覆う封止体とを有し、
前記第1ダイパッド及び前記第2ダイパッドの底面は前記封止体から露出され、
前記第1チップのパワートランジスタの出力用電極と電気的に接続された出力用ピンは、前記封止体の第1辺から突出され、
前記第2チップの駆動用回路と電気的に接続された制御用ピンは、前記封止体の前記第1辺と対向する第2辺から突出され、
前記第1ダイパッドと前記第2ダイパッドの対向する辺は、前記出力用ピンと前記制御用ピンとの間に位置することを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1チップ及び前記第2チップは、矩形形状に形成され、
前記第1チップ及び前記第2チップの長辺方向は、前記封止体の前記第1辺及び前記第2辺とに平行であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1チップの上に、前記パワートランジスタの出力用電極が設けられ、
前記出力用電極と前記出力用ピンとが、板状電極で接続されていることを特徴とする半導体装置。 - 請求項3記載の半導体装置において、
前記板状電極は、櫛歯状であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2チップの上に、駆動用回路の制御用電極が設けられ、
前記制御用電極と前記制御用ピンとが、ワイヤで接続されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記パワートランジスタは、MOSFETに形成され、
前記出力用電極は、ソース電極であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1ダイパッド、前記第2ダイパッド、前記出力用ピン、前記制御用ピンは、同一リードフレームから形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1ダイパッドの端部の最上部は、前記第1チップの最上部より高く、
前記第2ダイパッドの端部の最上部は、前記第2チップの最上部より高く、それぞれ形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
複数の前記出力用ピンは、前記封止体から露出され、
複数の前記出力用ピンは、前記封止体内部で連結されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1ダイパッド及び前記第2ダイパッドは、前記制御用ピン及び前記出力用ピンより厚く形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記封止体の前記第1辺及び前記第2辺とに交差する第3辺に対して、
前記第3辺と平行な前記第1ダイパッドの第1端面が、前記封止体の前記第3辺より内側に位置することを特徴とする半導体装置。
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US20120261825A1 (en) | 2012-10-18 |
US8232629B2 (en) | 2012-07-31 |
US20080054422A1 (en) | 2008-03-06 |
JP5390064B2 (ja) | 2014-01-15 |
US9129979B2 (en) | 2015-09-08 |
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